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| 8 - channel, 24 - bit , simultaneous sampling adc data sheet ad7770 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 2016 2017 analog devices, inc. all rights reserved. technical support www.analog.com features 8 - c hannel , 24- bit simultaneous sampling analog - to - digital converter (adc) single - ended or true differential inputs programmable gain amplifier (pga) per channel (gains of 1, 2, 4, and 8) low dc input current 4 na (differential) and 8 na (single - ended) up to 32 ksps outp ut data rate (odr) per channel programmable odrs and bandwidth sample rate converter ( src) for coherent sa mpling sampling rate resolution up to 15.2 10 ? 6 sp s low latency sinc3 filter path adjustable phase synchronization internal 2.5 v reference two power modes o ptimiz ing power dissipation and performance : h igh resolution mode and low power mode low resolution successive approx imation register (s ar) adc for system and chip diagnostic s power supply bipolar (1.65 v) or unipolar (3.3 v ) supplies digital input/output ( i / o ) supply: 1.8 v to 3.6 v performance temperature range: ? 40c to +105c functional temperature range: ? 40c to +125c performance combined ac a nd dc p erformance 1 03 db dynamic range at 32 ksps in high resolution mode ? 109 db total harmonic distortion ( thd ) 9 ppm of fsr integral nonlinearity ( inl ) 15 v offset error 0.1% fs gain error 10 ppm/c typ ical temperature coefficient applications protection r elays general - p urpose data acquisition industrial process control general description the ad7770 is an 8 - channel, simultaneous sampling adc. e ight full sigma - delta ( - ) adcs are on chip. the ad7770 provides a low input current to a llow direct sensor connection. each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitud e sensor outputs into the full - scale adc input range, maximizing the dynamic range of the signal chain. the ad7770 accepts a v ref voltage from 1 v up to 3.6 v. the analog inp uts accept unipolar (0 v to v ref ) or true bipolar ( v ref /2 ) analog input signals with 3.3 v or 1.65 v analog supply voltages, respectively for pga gain = 1 . t he analog inpu ts can be configured to accept true differential , pseudo differential , or single - ended signals to match different sensor output configurations. e ach channel conta ins a pga, an adc modulator and a sinc3, low latency digital filter. an src is provided to allow fine resolution control over the ad7770 odr. this control can be used in applications where the odr resolution is required to maintain coherency with 0.01 hz changes in the line frequency. the src is programmable through the serial port interface (spi ). the ad7770 implements two different interfaces: a data output interface and spi control interface. the adc data output interfac e is dedicated to transmitting the adc conversion results from the ad7770 to the processor. the spi write s to and read s from the ad7770 configuration registers and for the control and reading of data from the sar adc. the spi can also be configured to output the - conversion data. the ad7770 includes a 12 - bit sar adc. this adc can be used for ad7770 diagnostics without having to decommission one of the - adc channels dedicated to system measuremen t functions . with the use of an external multiplexer, which can be controlled through the three general - purpose input/output pins (gpios), and signal conditioning, the sar adc can validate the - adc measurements in applications where functional safety is required. in addition, the ad7770 sar adc includes an internal multiplexer to sense internal nodes. the ad7770 contains a 2.5 v reference and reference bu ffer. the reference has a typical temperature coefficient of 10 ppm/c. the ad7770 offers two modes of operation: high resolution mode and low power mode. high resolut ion mode provides a higher dynamic range while consuming 10.75 mw per channel; low power mode consumes just 3.37 mw pe r channel at a reduced dynamic range specification. the specified operating temperature range is ?40c t o +105c, although the device is operational up to +125c. note that throughout this data sheet, certain terms are used to refer to either the m ultifunction pins or a range of pins. the multi - function pins, such as dclk0/sdo, are referred to either by the entire pin name or by a single function of the pin, for example, dclk0, when only that function is relevant. in the case of range s of pins, avssx refer s to the following pins: avss1a, avss1b, avss2a, avss2b, avss3, and avss4.
ad7770* product page quick links last content update: 08/30/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7770 / ad7771 / ad7779 evaluation board documentation application notes ? an-1388: coherent sampling for power quality measurements using the ad7779 24-bit simultaneous sampling sigma-delta adc ? an-1392: how to calculate offset errors and input impedance in adc converters with chopped amplifiers ? an-1393: translating system level protection and measurement requirements to adc specifications ? an-1405: diagnostic features on the ad7770 and ad7779 data sheet ? ad7770: 8-channel, 24-bit, simultaneous sampling adc data sheet user guides ? ug-884: evaluating the ad7770, ad7771, and ad7779 8- channel, 24-bit, simultaneous sampling, sigma-delta adcs with power scaling software and systems requirements ? ad7770/ad7771/ad7779 - no-os driver tools and simulations ? ad7770 crc calculator ? ad7770/ad7771/ad7779 filter model ? ad7770/ad7771/ad7779 ibis model reference materials press ? analog devices improves monitoring and protection of smart grid transmission and distribution equipment design resources ? ad7770 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7770 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified. ad7770 data sheet rev. c | page 2 of 97 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 4 functional block diagram .............................................................. 5 specifications ..................................................................................... 6 doutx timing characterististics ........................................... 10 spi timing characterististics ................................................... 11 synchronization pins and reset timing characteristics ...... 12 sar adc timing characterististics ....................................... 13 gpio src update timing characterististics ......................... 13 absolute maximum ratings .......................................................... 14 thermal resistance .................................................................... 14 esd caution ................................................................................ 14 pin configuratio n and function descriptions ........................... 15 typical performance characteristics ........................................... 18 terminology .................................................................................... 31 theory of operat ion ...................................................................... 33 analog inputs .............................................................................. 33 transfer function ....................................................................... 34 core signal chain ....................................................................... 35 capacitive pga ........................................................................... 35 internal reference and reference buffers ............................... 35 integrated ldos ......................................................................... 36 clocking and sampling .............................................................. 36 digital reset and synchronization pins .................................. 36 digital filtering ........................................................................... 37 shutdown mode .......................................................................... 37 controlling the ad7770 ............................................................ 38 pin control mode ....................................................................... 38 spi control .................................................................................. 40 digital spi .................................................................................... 43 rms noise and resolution ............................................................ 46 high resolution mode ............................................................... 46 low power mode ........................................................................ 46 diagnostics an d monitoring ......................................................... 47 self diagnostics error ................................................................ 47 monitoring using the ad7770 sar adc (spi control mode) ........................................................................................... 48 - adc diagnostics (spi control mode) ............................ 50 - ? output data ............................................................................. 51 adc conversion output header and data ........................ 51 src (spi control mode) ........................................................... 52 data output interface ................................................................ 53 calculating the crc checksum .............................................. 58 register summary .......................................................................... 60 register details ............................................................................... 64 channel 0 configuration register ........................................... 64 channel 1 configuration register ........................................... 64 channel 2 configuration register ........................................... 65 channel 3 configuration register ........................................... 65 channel 4 configuration register ........................................... 66 channel 5 configuration register ........................................... 66 channel 6 configuration register ........................................... 67 channel 7 configuration register ........................................... 67 disable clocks to adc channel regist er .............................. 68 channel 0 sync offset register ................................................ 68 channel 1 sync offset register ................................................ 68 channel 2 sync offset register ................................................ 68 channel 3 sync offset register ................................................ 69 channel 4 sync offset register ................................................ 69 channel 5 sync offset register ................................................ 69 channel 6 sync offset register ................................................ 69 channel 7 sync offset register ................................................ 69 general user configuration 1 register ................................... 70 general user configuration 2 register ................................... 70 general user configuration 3 register ................................... 71 data output format register ................................................... 72 main adc meter and reference mux control register ...... 73 global diagnostics mux register ............................................. 74 gpio configuration register ................................................... 74 gpio data register .................................................................... 75 buffer configuration 1 register ............................................... 75 buffer configuration 2 register ............................................... 75 channel 0 offset upper byte register ..................................... 76 channel 0 offset middle byte register ................................... 76 channel 0 offset lower byte register ..................................... 76 channel 0 gain upper byte register ....................................... 76 channel 0 gain middle byte register ..................................... 76 channel 0 gain lower byte register ....................................... 77 data sheet ad7770 rev. c | page 3 of 97 channel 1 offset upper byte register ..................................... 77 channel 1 offset middle byte register .................................... 77 channel 1 offset lower byte register ..................................... 77 channel 1 gain upper b yte register ........................................ 78 channel 1 gain middle byte register ...................................... 78 channel 1 gain lower byte register ........................................ 78 channel 2 offset upper byte register ..................................... 78 channel 2 offset middle byte register .................................... 78 channel 2 offset lower byte register ..................................... 79 channel 2 gain upper byte register ........................................ 79 channel 2 gain middle byte register ...................................... 79 channel 2 gain lower byte register ........................................ 79 channel 3 offset upper byte register ..................................... 79 channel 3 offset middle byte register .................................... 80 channel 3 offset lower byte register ..................................... 80 channel 3 gain upper byte register ........................................ 80 channel 3 gain middle byte register ...................................... 80 channel 3 gain l ower byte register ........................................ 80 channel 4 offset upper byte register ..................................... 81 channel 4 offset middle byte register .................................... 81 channel 4 offset lower byte register ..................................... 81 channel 4 gain upper byte register ........................................ 81 channel 4 gain middle byte register ...................................... 81 channel 4 gain lower byte register ........................................ 82 channel 5 offset upper byte register ..................................... 82 channel 5 offset middle byte register .................................... 82 channel 5 offset lower byte register ..................................... 82 channel 5 gain upper byte register ........................................ 82 channel 5 gain middle byte register ...................................... 83 channel 5 gain lower byte register ........................................ 83 channel 6 offset upper byte register ..................................... 83 channel 6 offset middle byte register .................................... 83 channel 6 offset lower byte register ..................................... 83 channel 6 gain upper byte register ........................................ 84 channel 6 gain middle byte register ...................................... 84 channel 6 gain lower byte register ....................................... 84 channel 7 offset upper byte register ..................................... 84 channel 7 offset middle byte register .................................... 84 channel 7 offset lower byte register ..................................... 85 channel 7 gain upper byte register ....................................... 85 channel 7 gain middle byte register ...................................... 85 channel 7 gain lower byte register ....................................... 85 channel 0 status register .......................................................... 86 channel 1 status register .......................................................... 86 channel 2 status register .......................................................... 87 channel 3 status register .......................................................... 87 channel 4 status register .......................................................... 88 channel 5 status register .......................................................... 88 channel 6 status register .......................................................... 89 channel 7 status register .......................................................... 89 channel 0/chan nel 1 dsp errors register .............................. 90 channel 2/channel 3 dsp errors register .............................. 90 channel 4/channel 5 dsp errors register .............................. 91 channel 6/channel 7 dsp errors register .............................. 91 channel 0 to channel 7 error register enable register ....... 92 general errors register 1 ........................................................... 92 general errors register 1 enable .............................................. 93 general errors register 2 ........................................................... 93 general errors register 2 enable .............................................. 94 error status register 1 ................................................................ 94 error status register 2 ................................................................ 95 error status register 3 ................................................................ 95 decimation rate (n) msb register ......................................... 95 decimation rate (n) lsb register ........................................... 96 decimation rate (if) msb register ......................................... 96 decimation rate (if) lsb register .......................................... 96 src load source and load update register .......................... 96 outline dimensions ........................................................................ 97 ordering guide ........................................................................... 97 ad7770 data sheet rev. c | page 4 of 97 revision history 8 /2017 rev. b to rev. c changes to features section and general description section ....... 1 change to start pin description, table 9 ................................ 15 changes to figure 48 ...................................................................... 2 4 change to digital reset and synchronization pins section and internal reference and reference buffers section ..................... 36 change to figure 95 ....................................................................... 37 changes to phase adjustment section and table 16 ................. 41 added table 17 renumbered sequentially ................................ 41 change to digital spi sec tion ....................................................... 43 change to table 25 ......................................................................... 46 10 /2016 rev. a to rev. b changes to figure 45 ...................................................................... 24 chang es to figure 56, figure 59 , and figure 61 ......................... 26 c hanges to figure 72 and figure 73 ............................................. 28 changes to figure 76 ...................................................................... 29 added figur e 82 renumbered sequentially .............................. 30 changes to figure 86 to figure 89 ................................................ 34 changes to spi transmission erro rs (spi control mode) section .............................................................................................. 48 changes to table 33 and table 34 ................................................ 51 changes to src group delay and latency section and settling time section ................................................................................... 53 changes to table 39 and table 40 ................................................ 57 changes to calculating the crc checksum section and table 42 ............................................................................................ 58 changes to ordering guide .......................................................... 9 7 5/ 20 16 rev. 0 to rev. a change to features ............................................................................ 1 changes to table 1 ............................................................................. 6 changes to figure 33 a nd figure 3 6 ............................................ 21 change to figure 78 ....................................................................... 28 4 / 20 16 revision 0 : initial version data sheet ad7770 rev. c | page 5 of 97 functional block dia gram avdd1x ref_out refx+ vcm avdd2 avssx avdd4 convst_sar iovdd aregxcap dregcap clock manager xtal1 xtal2/mclk sync_in sync_out start refxC dclk drdy dout3 dout2 dout1 dout0 format1 format0 mode3/alert mode2/gpio2 mode1/gpio1 mode0/gpio0 alert/cs dclk2/sclk dclk1/sdi dclk0/sdo reset - adc ain0+ ain0C 280mv p-p - adc references ext_ref int_ref ain1+ ain1C - adc references ain2+ ain2C - adc references ain3+ ain3C - adc references ain4+ ain4C - adc references ain5+ ain5C references ain6+ ain6C references diagnostic inputs ain7+ ain7C sinc3/ src filter gain offset common- mode voltage analog ldo 2.5v ref sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset - adc - adc auxain+ auxainC data output interface register map and logic control hardware mode configuration spi interface ad7770 sar adc digital ldo pga pga pga pga pga pga pga pga 12538-001 figure 1. ad7770 data sheet rev. c | page 6 of 97 specifications av dd1x = 1.65 v, avssx 1 = ? 1.65 v ( dual supply operation) , avdd1x = 3.3 v, av s s x = analog ground ( agnd ) ( single - supply op eration) , avdd2 x ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, r e f x+/refx? = 2.5 v (internal/external ), master clock ( mclk ) = 8192 khz for high resolution mode and 4096 khz for low p ower mode , odr = 32 ksps for high resolution mode and 8 ksps for low power mode ; all specifications at t min to t max , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit analog inputs diffe rential input voltage range v ref = (refx+ ? refx?) v ref /pga gain v single - ended input voltage range 0 to v ref /pga gain v ainx common - mode input range avssx + 0.10 (avdd1x + avssx)/2 avdd1x ? 0.10 v absolute ainx voltage limits avssx + 0.10 avdd1x ? 0.10 v dc input current differential high resolution, mclk = 8192 khz 4 na low power mode, mclk = 4096 khz 1 na single - ended high resolution, mclk = 8192 khz 8 na low power mode, mclk = 4096 khz 2 na input current drift 50 pa/c ac input capacitance 8 pf pga gain settings , pga gain 1, 2, 4, or 8 bandwidth small signal, high resolution mode 2 mhz small signal, low power mode 512 khz large signal, high resolution mode 5 khz large signal, low power mode 1.5 khz reference internal initial accuracy ref_out, t a = 25c 2.495 2.5 2.505 v temperature coefficient 10 38 ppm/c reference load current, i l ? 10 +10 ma dc power supply rejection line regulation 95 db load regulation, ?v out /?i l 100 v/ma voltage noise, e n p -p 0.1 hz to 10 hz 6.8 v rms voltage noise density, e n 1 khz, 2.5 v reference 273.5 nv/hz turn on settling time 100 nf 1.5 ms external input voltage v ref = (refx+ ? refx?) 1 2.5 avdd1x v buffer headroom avssx + 0.1 avdd1x ? 0.1 v refx? input voltage avssx avdd1x ? refx+ v average refx input current current per channel reference buffer disabled, high resolution mode 18 a/v reference buffer precharge mod e (pre - q), high resolution mode 600 na/v reference buffer disabled, low power mode 4.5 a/v r eference buffer pre - q, low power mode 100 na/v reference buffer enabled, high resolution mode 12 na/v reference buffer enabled, low power mode 5 na/v data sheet ad7770 rev. c | page 7 of 97 parameter test conditions/comments min typ max unit temperature range specified performance t min to t max ? 40 +105 c functional 2 t min to t max ? 40 +125 c temperature sensor accuracy 2 c digital filter response (sinc3) group delay see the src group delay section settling time see the settling time section pass band ? 0.1 db see the src bandwidth section ? 3 db see the src bandwidth section decimation rate 64 4095.99 clock source frequency high resolution mode 0.655 8.192 mhz low power mode 1.3 4.096 mhz duty cycle 45:55 50:50 55:45 % - adc speed and performance resolution 24 bits odr high resolution mode 32 ksps low power mode 8 ksps no missing codes up to 24 ksps 24 bits ac accuracy dynamic range shorted inputs, pga gain = 1 32 ksps high resolution mode 103 db 8 ksps high resolution mode 113 db low power mode 103 db 2 ksps low power mode 113 db thd ? 0.5 dbfs, high resolution mode ? 109 db ? 0.5 dbfs, low power mode ? 105 db signal - to - noise - and - distortion ratio (sinad) f in = 60 hz 106 db sfdr high resolution mode, 16 ksps, pga gain = 1 132 db intermodulation distortion (imd) f a = 50 hz, f b = 51 hz, high resolution mode ? 125 db f a = 50 hz, f b = 51 hz, low power mode ? 105 db dc power supply rejection avdd1x = 3.3 v ? 90 db dc common - mode rejection ratio 80 db crosstalk ? 120 db dc accuracy inl high resolution mode endpoint method, pga gain = 1 8 15 ppm of fsr other pga gains 4 15 ppm of fsr low power mode endpoint method, pga gain = 1 9 17 ppm of fsr other pga gains 6 15 ppm of fsr offset error 15 90 v offset error drift 0.25 v/c over time ?2 v/ 1000 hours ad7770 data sheet rev. c | page 8 of 97 parameter test conditions/comments min typ max unit offset matching 25 v gain error 0.1 % fs gain drift vs. temperature 0.7 5 ppm/c gain matching 0.1 % sar adc speed and performance resolution 12 bits analog input range avss4 + 0.1 avdd4 ? 0.1 v analog input common - mode range avss4 + 0.1 (avdd4 + avss4)/2 avdd4 ? 0.1 v analog input dynamic current 256 ksps, 0 dbfs 100 na throughput 256 ksps dc accuracy differential mode inl 1.5 lsb dnl no missing codes (12 - bit) ? 0.99 +1 lsb offset 1 lsb gain 12 lsb ac performance snr 1 khz 66 db thd 1 khz ? 81 db vcm pin output (avdd1x + avssx)/2 v load current, i l 1 ma load regulation, ?v out /?i l 12 mv/ma short - circuit current 5 ma logic inputs input voltage high, v ih 0.7 iovdd v low, v il 0.4 v hysteresis 0.1 v input currents ? 10 +10 a logic outputs 3 output voltage high, v oh iovdd 3 v, i source = 1 ma 0.8 iovdd v 2.3 v iovdd < 3 v, i source = 500 a 0.8 iovdd v iovdd < 2.3 v, i source = 200 a 0.8 iovdd v low, v ol iovdd 3 v, i sink = 2 ma 0.4 v 2.3 v iovdd < 3 v, i sink = 1 ma 0.4 v iovdd < 2.3 v, i sink = 100 a 0.4 v leakage current floating state ? 10 +10 a output capacitance floating state 10 pf - adc data output coding twos complement sar adc data output coding binary data sheet ad7770 rev. c | page 9 of 97 parameter test conditions/comments min typ max unit power supplies all - channels enabled avdd1x ? avssx 3.0 3.6 v i avdd1x 4 , 5 reference buffer pre - q, vcm enabled, internal reference enabled high resolution mode 18.5 23.7 ma low power mode 5 6.4 ma reference buffer enabled, vcm enabled, internal reference enabled high resolution mode 20.5 26.7 ma low power mode 5.5 7.1 ma reference buffer disabled, vcm disabled, internal reference disabled high resolution mode 14.3 18.8 ma low power mode 3.9 5.1 ma avdd2x ? avssx 2.2 3.6 v i avdd2x high resolution mode 9 9.45 ma low power mode 3.5 3.7 ma avdd4 ? avssx avdd1x ? 0.3 avdd1x v i avdd4 sar enabled 1.7 2 ma sar disabled 1 10 a avssxv ? dgnd ? 1.8 0 v iovdd ? dgnd 1.8 3.6 v i iovdd high resolution mode 8 11.3 ma low power mode 3 4.4 ma power dissipation 6 internal buffers bypassed, internal reference disabled, internal oscillator disabled, sar disabled high resolution mode 32 ksps 117 136 mw low power mode 8 ksps 38 44 mw power - down all adcs disabled 530 w 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b, avss3, and avss4 . this te rm is used throughout the data sheet. 2 at temperatures higher than 105c, the device can be operated normally, though slight degradation on the max imum /min imum specifications is expected because these specifications are only guarantee d up to 105c. see the typical performance characteristics section for plots showing the typical performance of the device at high temperature s. 3 the sdo pin and the doutx pin are configure d in the default mode of strength. 4 avdd1x = 3.3 v, avssx = gnd = ground, iovdd = 1.8 v, cmos clock. 5 disabling either th e vcm pin o r the internal reference results in a 40 a typical current consumption reduction. 6 power dissipation is calculated using the maximum supply voltage, 3.6 v. ad7770 data sheet rev. c | page 10 of 97 doutx timing characterististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd (single - supply operation) , a vdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, r e f x+/refx? = 2.5 v internal/external, mclk = 8192 khz ; all specifications at t min to t max , unless otherwise noted. table 2 . parameter description 2 test conditions /comments min typ max unit t 1 mclk frequency 50:50 0.655 8.192 mhz t 2 mclk low time 60 ns t 3 mclk high time 60 ns t 4 dclk high time mclk/2 121 ns t 5 dclk low time mclk/2 121 ns t 6 mclk falling edge to dclk rising edge 45 ns t 7 mclk falling edge to dclk falling edge 45 ns t 8 dclk rising edge to drdy rising edge 2 ns t 9 dclk rising edge to drdy falling edge 1 ns t 10 doutx setup time 20 ns t 11 doutx hold time 20 ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b, avss3, and avss4 . this te rm is used throughout the data sheet. 2 all input signals are speci fied wit h t r = t f = 1 n s/v (10% to 90% of io v dd ) and timed from a voltage level of (v il + v ih )/2. mclk dc lk drd y lsb msb msb C 1 lsb + 1 lsb doutx t 2 t 4 t 5 t 6 t 7 t 10 t 11 t 8 t 9 t 1 t 3 12538-002 figure 2 . data interface timing diagram data sheet ad7770 rev. c | page 11 of 97 spi timing characterististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, av d d2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, r e f x+/refx? = 2.5 v ( internal/external ) , mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 3. parameter description 2 test conditions/comments min typ max unit t 12 sclk p eriod 50:50 30 mhz t 13 sclk l ow time 7 ns t 14 sclk h igh time 7 ns t 15 sclk r ising edge to cs falling edge 10 ns t 16 cs f alling edge to sclk rising edge 10 ns t 17 sclk rising edge to cs rising edge 10 ns t 18 cs rising edge to sclk rising edge 10 ns t 19 minimum cs high time 10 ns t 20 sdi s etup time 5 ns t 21 sdi h old time 5 ns t 22a cs falling edge to sdo e nable (spi = mode 0) 30 ns t 22b sclk falling edge to sdo e nable (spi = mode 1) 49 ns t 23 sdo s etup time 10 ns t 24 sdo h old time 10 ns t 25 cs rising edge to sdo d isable 30 ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b, avss3, and avss4 . this te rm is used throughout the data sheet. 2 all input signals are spec ified with t r = t f = 1 ns/v (10% to 90% of i ovdd) and timed from a voltage level of (v il + v ih )/2. cs sclk msb msb C 1 lsb + 1 lsb sdi msb msb C 1 lsb + 1 lsb sdo t 15 t 16 t 13 t 14 t 20 t 22a t 21 t 24 t 23 t 22b t 12 t 19 t 17 t 18 t 25 12538-003 figure 3 . spi control interface timing diagram ad7770 data sheet rev. c | page 12 of 97 synchronization pins an d reset timing characteristics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, av dd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, r e f x+/refx? = 2.5 v ( internal/external ) , mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 4 . parameter description 2 test conditions/comments min typ max unit t 26 start s etup time 10 ns t 27 start h old time mclk ns t 28 mclk f alling e dge to sync_out f alling edge mclk ns t 29 sync_in s etup time 10 ns t 30 sync_in h old time mclk ns t init_ sync_in sync_in r ising edge to f irst drdy 16 ksps, high resolution mode 145 s t init_ reset reset r ising edge to f irst drdy 16 ksps, high resolution mode 225 s t 31 reset h old time 2 mclk ns t power_up start time t power_up is not shown in figure 4 2 ms 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b, avss3, and avss4 . this te rm is used throughout the data sheet. 2 all input signals a re specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih ) /2. mclk start sy nc _out sy nc _in drd y reset t 26 t 27 t 28 t 29 t init_ sy nc _in t 31 t init_r ese t t 30 12538-004 figure 4. synchronization pins and reset control interface timing diagram data sheet ad7770 rev. c | page 13 of 97 sar adc timing characterististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, a vdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external) , mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 5 . parameter description 2 min typ max unit t 32 conversion time 1 3.4 s t 33 acquisition time 3 500 ns t 34 delay time 50 ns t 35 throughput d ata rate 256 ksps 1 avssx refers to the following pins: avss1a, avss1b, avss2 a, avss2b, avss3 and avss4. this term is used throughout the data sheet. 2 all input signals are specifie d with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage le vel of (v il + v ih )/ 2. 3 direct mode enabled. if deglitch mode is enabled, add 1.5 /mclk as described in table 30 . cs convst_sar t 33 t 32 t 35 t 34 12538-005 figure 5 . sar adc timing diagram gp io s rc update timing characterististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd , a vdd2 ? avs sx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external) , mclk = 8192 khz; all specifications t min to t max , unless otherwise noted. table 6 . parameter description 2 min typ max unit t 36 gpio2 s etup time 10 ns gpio2 h old time t 37 high r esolution m ode mclk ns t 37 low p ower mode 2 mclk t 38 mclk r ising e dge to gpio1 rising edge time 20 ns t 39 gpio0 setup time 5 ns t 40 gpio0 hold time mclk ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b, avss3 and avss4 . this term is used throughout the data sheet. 2 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of io v dd ) and timed from a voltage level of (v il + v ih )/ 2. mclk gpio2 gpio1 gpio0 t 36 t 37 t 38 t 39 t 40 12538-006 figure 6 . gpios for src update timing diagram ad7770 data sheet rev. c | page 14 of 97 a bsolute maximum rati ngs table 7 . parameter rating any supply pin to avssx ? 0.3 v to +3.96 v avssx to dgnd ? 1.98 v to +0.3 v a regxcap to avssx ? 0.3 v to +1.98 v d regcap to dgnd ? 0.3 v to +1.98 v iovdd to dgnd ? 0.3 v to +3.96 v iovdd to avssx ? 0.3 v to +5.94 v avdd 4 to avssx avdd1x ? 0.3 v to 3.96 v analog input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) refx input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) aux a in avssx ? 0.3 v to avdd4 + 0.1 v or 3.96 v (whichever is less) digital input voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) digital output voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) xtal1 to dgnd dgnd ? 0.3 v to d regcap + 0.3 v or 1.98 v (whichever is less) ainx, auxain, and digital input current 10 ma operating temperature range ? 40c to +125c junction temperature, t j maximum 150c storage temperature range ? 65c to +150c reflow soldering 260c esd 2 kv f ield induced charged device model (f icdm ) 500 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect produ ct reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. close attention to pcb thermal design is required. table 8 . thermal resistance package type 1 ja j b jt jb unit 64- lead lfcsp no thermal vias 30.43 n/a 2 0.13 6.59 c/w 49 thermal vias 22.62 3.17 0.09 3.19 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51. 2 n/a means not applicable. esd caution data sheet ad7770 rev. c | page 15 of 97 pin configuration and fu nction descriptions ad7770 top view (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 convst_sar alert/cs dclk2/sclk dclk1/sdi dclk0/sdo dgnd dregcap iovdd dout3 dout2 dout1 dout0 dclk drdy xtal1 xtal2/mclk 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 auxain? auxain+ avdd4 avss4 avss2a areg1cap avdd2a vcm clk_sel format0 format1 avss3 avdd2b areg2cap avss2b ref_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain0? ain0+ ain1? ain1+ avss1a avdd1a ref1? ref1+ ain2? ain2+ ain3? ain3+ mode0/gpio0 mode1/gpio1 mode2/gpio2 mode3/alert notes 1. exposed pad. connect the exposed pad to avssx. ain4? ain4+ ain5? ain5+ avss1b avdd1b ref2? ref2+ ain6? ain6+ ain7? ain7+ reset sync_in sync_out start 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 12538-007 figure 7. pin configuration table 9. pin function descriptions pin no. mnemonic type direction description 1 ain0? analog input input analog input channel 0, negative. 2 ain0+ analog input input analog input channel 0, positive. 3 ain1? analog input input analog input channel 1, negative. 4 ain1+ analog input input analog input channel 1, positive. 5 avss1a supply supply negative front-end analog supply for channel 0 to channel 3, typical at ?1.65 v (dual supply) or agnd (single supply). connect all the avssx pins to the same potential. 6 avdd1a supply supply positive front-end analog supply for channel 0 to channel 3, typical at avssx + 3.3 v. connect this pin to avdd1b. 7 ref1? reference input negative reference input 1 for channel 0 to channel 3, typical at avssx. connect all the refx? pins to the same potential. 8 ref1+ reference input positive reference input 1 for channel 0 to channel 3, typical at ref1? + 2.5 v. 9 ain2? analog input input analog input channel 2, negative. 10 ain2+ analog input input analog input channel 2, positive. 11 ain3? analog input input analog input channel 3, negative. 12 ain3+ analog input input analog input channel 3, positive. 13 mode0/gpio0 digital i/o i/ o mode 0 input in pin control mode (mode0). see table 14 for more details. configurable general-purpose input/output 0 in spi control mode (gpio0). if not in use, connect this pin to dgnd or iovdd. 14 mode1/gpio1 digital i/o i/ o mode 1 input in pin control mode (m ode1). see table 14 for more details. configurable general-purpose input/output 1 in spi control mode (gpio1). if not in use, connect this pin to dgnd or iovdd. ad7770 data sheet rev. c | page 16 of 97 pin no. mnemonic type direction description 15 mode2/gpio2 digital i/o i/o mode 2 input in pin control mode (mode2). see table 14 for more details. configurable general - purpose input/output 2 in spi control mode (gpio2). if not in use, connect this pin to dgnd or iovdd. 16 mode3/alert digital i/o i / o mode 3 in put in pin control mode (mode3). see table 14 for more details. alert output in spi control mode (alert) . 17 convst_sar digital input input - output interface selection pin in pin control mode. s ee table 13 for more details . this pin also functions as the start for the sar conversion in spi control mode. 18 alert/ cs digital input input alert output in pin control mode (alert). chip select in spi control mode ( cs ). 19 dclk2 / sclk digital input input dclk frequency selection pin 2 in pin control mode (dclk2). s ee table 15 for more details . spi clock in spi control mode (sclk). 20 dclk1 / sdi digital input input dclk frequency selection pin 1 in pin control mode (dclk1). s ee table 15 for more details . spi data input in spi control mode (sdi). connect this pin to dgnd if the device is configured in pin control mode with the spi as the data output interface. 21 dclk0 / sdo digital output output dclk frequency selection pin 0 in pin control mode (dclk0). s ee table 15 for more details . spi data output in spi control mode (sdo). 22 dgnd supply supply digital ground. 23 dregcap supply output digital low dropout ( ldo ) output . decouple this pin to dgnd with a 1 f cap acitor. 24 iovdd supply supply digital levels input/output and digital ldo (dldo) supply from 1.8 v to 3.6 v. iovdd must not be lower than dregcap. 25 dout3 digital output i / o data output pin 3. if the device is configured in daisy - chain mode, this pin acts as an input pin. s ee the daisy - chain mode section for more details. 26 dout2 digital output i / o data output pin 2. if the device is configured in daisy - chain mode, this pin acts as an input pin. see the daisy - chain mode section for more details. 27 dout1 digital output output data output pin 1 . 28 dout0 digital output output data output pin 0 . 29 dclk digital output output data output clock . 30 drdy digital output output data output ready pin. 31 xtal1 clock input crystal 1 input connection. if cmos is used as a clock source, tie this pin to dgnd. see table 12 for more details . 32 xtal2/mclk clock input crystal 2 input connection (xtal2). see table 12 for more details. cmos clock (mclk). see table 12 for more details. 33 start digital input input synchronization pulse . this pin internally synchronize s an external start asynchronous pulse with mclk. the synchronize signal is shift ed out by the sync_out pin. if not in use, t ie this pin to iovdd . see the phase adjustment se cti on and the digital reset and synchronization pins section for more details. 34 sync_out digital output input synchronization signal . this pin generates a synchronous pulse generated and driven by hardware (via the st art pin) or by software (general_user_ config_2, bit 0 ). if this pin is in use, it must be wired to the sync_in pin. see the phase adjustment section and the digital reset and synchronization pins section for more details. 35 sync_in digital input input r eset for the internal digital block and synchronize for multiple devices . see the digital reset and synchronization pins section for more detail s. 36 reset digital input input asynchronous reset pin. this pin r esets all registers to their default value. it is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. 37 ain7+ analog input input analog input channel 7 , positive . 38 ain7? analog input input analog input channel 7 , negative . 39 ain6+ analog input input analog input channel 6 , positive . 40 ain6? analog input input analog input channel 6 , negative . 41 ref2+ reference input positiv e referenc e input 2 for channel 4 to channel 7 , typical at ref2? + 2.5 v . data sheet ad7770 rev. c | page 17 of 97 pin no. mnemonic type direction description 42 ref2? reference input negative reference input 2 for channel 4 to channel 7, typical at avssx. connect all the refx? pins to the same potential . 43 avdd1b supply supply positive front - end analog supply for channel 4 to channel 7. connect t his pin t o avdd1a . 44 avss1b supply supply negative front - end analog supply for channel 4 to channel 7, typical at ? 1.65 v (dual supply) or agnd (single supply). connect all the avssx pins to the same potential . 45 ain5+ analog input input analog input channel 5 , positive . 46 ain5? analog input input analog input channel 5 , negative . 47 ain4+ analog input input analog input channel 4 , positive . 48 ain4? analog input input analog input channel 4 , negative . 49 ref_out reference output 2.5 v reference output . connect a 100 nf capacitor on this pin if using the internal reference. 50 avss2b supply supply negative analog supply . connect all the avssx pins to the same potential . 51 areg2cap supply output analog ldo output 2 . decouple this pin to avss2 b with a 1 f cap acitor. 52 avdd2b supply supply positive analog supply. connect t his pin to avdd2a . 53 avss3 supply supply negative analog ground. connect all the avssx pins to the same potential . 54 format1 digital input input output data frame 1. s ee table 13 for more details . 55 format0 digital input input output data frame 0. s ee table 13 for more details . 56 clk_sel digital input input sel ect clock source. s ee table 12 for more details . 57 vcm analog output output common - mode voltage output, typical at ( avdd1 + avss x ) /2 . 58 avdd2a supply input analog supply from 2.2 v to 3.6 v. avss2x must not be lower than aregxcap . connect t his pin to avdd2b . 59 areg1cap supply output analog ldo output 1 . decouple this pin to avss x with a 1 f capacitor. 60 avss2 a supply input negative analog supply. connect all the avssx pins to the same potential . 61 avss4 supply supply neg ative sar analog supply and reference . connect all avssx pin s to the same potential . 62 avdd4 supply supply positive sar analog supply and reference source. 63 auxain+ analog input input positive sar analog input channel . 64 auxain? analog input input negative sar analog input channel . epad supply input exposed pad. connect the exposed pad to avssx . ad7770 data sheet rev. c | page 18 of 97 typical performance characteristics C10 C8 C6 C4 C2 0 2 4 10 8 6 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 ch 3 ch 2 ch 1 ch 0 ch 4 ch 5 ch 6 ch 7 12538-208 fig ure 8 . inl vs. input voltage and channel at 16 ksps, high resolution mode C10 C8 C6 C4 C2 0 2 4 10 8 6 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c v ref = 2.5v differential v in gain v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 12538-209 figure 9 . inl vs . input voltage and pga gain at 16 ksps, high resolution mode C12 C10 C8 C6 C4 C2 0 2 4 10 8 6 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = C40c t a = +25c t a = +105c t a = +125c 12538-210 figure 10 . inl vs . input voltage and temperature at 16 ksps , high resolution mode C15 C10 C5 0 5 10 15 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 ch 3 ch 2 ch 1 ch 0 ch 4 ch 5 ch 6 ch 7 12538-2 1 1 figure 11 . inl vs. input voltage and channel at 4 ksps, low power mode C15 C10 C5 0 5 10 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c v ref = 2.5v differential v in gain v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 12538-212 figure 12 . inl vs. input voltage and pga gain at 4 ksps , low power mode C15 C10 C5 0 5 10 15 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = C40c t a = +25c t a = +105c t a = +125c 12538-213 figure 13 . in l vs . input voltage and temperature at 4 ksps , low power m ode data sheet ad7770 rev. c | page 19 of 97 C20 C15 C10 C5 0 5 10 20 15 C4 C3 C2 C1 0 1 2 3 4 inl (ppm) input voltage (v) temperature = 25c gain = 1 differential input signal v cm = (avdd1x + avssx) 2 v ref = 1v v ref = 1.5v v ref = 2v v ref = 2.5v v ref = 3v v ref = 3.3v 12538-214 figure 14 . inl vs . input voltage and reference voltage (v ref ) at 16 ksps , high resolution mode C10 C6 C2 2 6 C8 C4 0 4 8 10 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c v ref = 2.5v differential input signal gain = 1 v cm = 1.35v v cm = 1.65v v cm = 1.95v 12538-215 figure 15 . inl vs . input voltage and v cm at 16 ksps, high resolution mode 0 200 400 600 800 1000 1200 1400 sample count adc code v ref = 2.5v v cm = (avdd1x + avssx) 2 temperature = 25c 8388212 8388256 8388300 8388344 8388388 8388432 8388476 8388520 8388564 8388608 8388652 gain = 1 gain = 2 gain = 4 gain = 8 12538-216 figure 16 . noise histogram at 16 ksps, high resolution mode C20 C15 C10 C5 0 5 10 20 15 C4 C3 C2 C1 0 1 2 3 4 inl (ppm) input voltage (v) temperature = 25c gain = 1 differential input signal v cm = (avdd1x + avssx) 2 v ref = 1v v ref = 1.5v v ref = 2v v ref = 2.5v v ref = 3v v ref = 3.3v 12538-217 figure 17 . inl vs . input voltage and v ref at 4 ksps , low power mode C15 C5 5 C10 0 10 15 C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 in l (ppm) input vo lt age (v) temperature = 25c v ref = 2.5v differential input signal gain =1 v cm = 1.35v v cm = 1.65v v cm = 1.95v 12538-218 figure 18 . inl vs . input voltage and v cm at 4 ksps, low power mode 0 200 400 600 800 1000 1200 1400 sample count adc code v ref = 2.5v v cm = (avdd1x + avssx) 2 temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 8388164 8388204 8388244 8388284 8388324 8388364 8388404 8388444 8388484 8388524 8388564 8388604 8388644 12538-219 figure 19 . noi se histogram at 4 ksps, low power mode ad7770 data sheet rev. c | page 20 of 97 0 1 C40 25 105 125 2 3 4 5 6 7 8 noise (v rms) temperature (c) v ref = 2.5v v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 12538-220 figure 20 . noise vs. temperature at 16 ksps , high resolution mode 335360 652800 970240 1287680 1605120 1922560 2240000 2557440 2874880 3192320 3509760 3827200 4144640 4462080 4779520 5096960 5414400 5731840 6049280 6366720 6684160 7001600 7319040 7636480 7953920 0 1 2 3 4 5 6 7 noise (v rms) clock frequency (hz) v ref = 2.5v v cm = (avdd1x + avssx) 2 temperature = 25c decimation = 256 gain = 1 gain = 2 gain = 4 gain = 8 12538-221 figure 21 . noise vs. clock frequency, high resolution mode 0 20 40 60 80 100 120 140 noise (nv/hz) odr (sps) 2000 4000 8000 16000 32000 gain = 1 gain = 2 gain = 4 gain = 8 12538-222 figure 22 . noise vs. odr, high resolution mode 0 1 C40 25 105 125 2 3 4 5 6 7 8 noise (v rms) temperature (c) v ref = 2.5v v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 12538-223 figure 23 . noise vs. temperature at 4 ksps, low power mode 0 1 2 3 4 5 6 7 noise (v rms) clock frequency (hz) v ref = 2.5v v cm = (avdd1x + avssx) 2 temperature = 25c decimation = 256 gain = 1 gain = 2 gain = 4 gain = 8 294400 448000 601600 755200 908800 1062400 1216000 1369600 1523200 1676800 1830400 1984000 2137600 2291200 2444800 2598400 2752000 2905600 3059200 3212800 3366400 3520000 3673600 3827200 3980800 12538-224 figure 24 . noise vs. clo ck frequency, low power mode 0 50 100 150 200 250 300 noise (nv/hz) odr (sps) 500 1000 2000 4000 8000 gain = 1 gain = 2 gain = 4 gain = 8 12538-225 figure 25 . noise vs. odr, low power mode data sheet ad7770 rev. c | page 21 of 97 amplitude (db) frequency (hz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 656.250000 1296.875000 1986.328125 2617.187500 3250.000000 3884.765625 4156.250000 4789.062500 5427.734375 6066.406250 6703.125000 7312.500000 7921.875000 8531.250000 9140.625000 9750.000000 10359.375000 10968.750000 11578.125000 12187.500000 12796.875000 13406.250000 14015.625000 14625.000000 15234.375000 15843.750000 gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 50hz 16384 samples 32ksps 12538-226 figure 26. fft at 32 ksps, high resolution mode, input frequency (f in ) = 50 hz amplitude (db) frequency (hz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 1khz 16384 samples 32ksps 0 1103.515625 2234.375000 3304.687500 4388.671875 5462.890625 6533.203125 7648.437500 8562.500000 9632.812500 10703.125000 11773.437500 12843.750000 13914.062500 14984.375000 12538-227 figure 27. fft at 32 ksps, high resolution mode, input frequency (f in ) = 1 khz ?130 ?125 ?120 ?115 ?110 ?105 ? 100 thd (db) input frequency (hz) v in =?0.5dbfs v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 10 109 208 307 406 505 604 703 802 901 1000 1700 2400 3170 3870 4710 5620 6320 7160 7860 12538-228 figure 28. thd vs. input frequency at 16 ksps, high resolution mode amplitude (db) frequency (hz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 50hz 8192 samples 8ksps 0 261.71875 523.43750 785.15625 1046.87500 1308.59375 1570.31250 1832.03125 2093.75000 2355.46875 2617.18750 2878.90625 3140.62500 3402.34375 3664.06250 3925.78125 12538-229 figure 29. fft at 8 ksps, low power mode, input frequency (f in ) = 50 hz amplitude (db) frequency (hz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 1khz 8192 samples 8ksps 0 273.4375 546.8750 820.3125 1093.7500 1367.1875 1640.6250 1914.0625 2187.5000 2460.9375 2734.3750 3007.8125 3281.2500 3554.6875 3828.1250 12538-230 figure 30. fft at 8 ksps, low power mode, input frequency (f in ) = 1 khz ?130 ?125 ?120 ?115 ?110 ?105 ? 100 thd (db) input frequency (hz) v in =?0.5dbfs v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 10.0 208.0 406.0 604.0 811.9 1010.0 1220.0 1440.0 1660.0 1870.0 12538-231 figure 31. thd vs. input frequency at 4 ksps, low power mode ad7770 data sheet rev. c | page 22 of 97 C140 C135 C130 C125 C120 C115 C110 C105 C100 thd (db) input voltage (v) input frequency = 50hz v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 12538-232 figure 32 . thd vs . input voltage at 16 ksps , high resolution mode C125 C120 C115 C110 C105 C100 C95 C90 thd (db) reference voltage (v) input frequency = 50hz input voltage = C0.5dbfs temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 12538-233 figure 33 . thd vs. reference voltage at 16 ksps, high resolution mode C125 C120 C115 C110 C105 C100 thd (db) mclk frequency (hz) 335360 970240 1605120 2240000 2874880 3509760 4144640 4779520 5414400 6049280 6684160 7319040 7953920 gain = 1 gain = 2 gain = 4 gain = 8 input frequency = 50hz v ref = 2.5v input voltage = C0.5dbfs temperature = 25c decimation = 256 12538-234 figure 34 . thd vs. mclk f requency , high resolution mode C140 C135 C130 C125 C120 C115 C110 C105 C100 thd (db) input voltage (v) input frequency = 50hz v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 12538-235 figure 35 . thd vs . input voltage at 4 k sps , low power mode C125 C120 C115 C110 C105 C100 C95 C90 thd (db) reference voltage (v) input frequency = 50hz input voltage = C0.5dbfs temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 12538-236 figure 36 . thd vs . reference voltage at 4 ksps , low power mode C130 C125 C120 C115 C110 C105 C100 thd (db) mclk frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 input frequency = 50hz v ref = 2.5v input voltage = C0.5dbfs temperature = 25c decimation = 256 167680 485120 802560 1120000 1437440 1754880 2072320 2389760 2707200 3024640 3342080 3659520 3976960 12538-237 figure 37 . thd vs. mclk f requency , low power mode data sheet ad7770 rev. c | page 23 of 97 85 125 120 115 110 105 100 95 90 snr (db) odr (khz) v in = 0dbfs v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 1 32 16 8 4 2 12538-238 figure 38 . snr vs. odr at 16 ksps, high resolution mode 95 100 105 1 10 1 15 120 dynamic range (db) pg a gain 1 2 4 8 temper a ture = 25c odr = 16ksps 12538-239 figure 39 . dynamic range vs. pga g ain , high resolution mode C35 C25 C30 C20 C15 C10 C5 0 1 2 4 8 offset error (v) pg a gain ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 temperature = 25c v in = 0v v ref = 2.5v avdd1x = 3.3v 12538-240 figure 40 . offset error vs . pga gain , high resolution mode 85 125 120 115 110 105 100 95 90 snr (db) odr (khz) v in = 0dbfs v ref = 2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 0.5 8 4 2 1 12538-241 figure 41 . snr vs. odr at 4 ksps, low power mod e 95 100 105 1 10 1 15 120 dynamic range (db) pg a gain 1 2 4 8 temper a ture = 25c odr = 4ksps 12538-242 figure 42 . dynamic ran ge vs. pga g ain , low power mode C35 C25 C30 C20 C15 C10 C5 5 0 1 2 4 8 offset error (v) pga gain ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 temperature = 25c v in = 0v v ref = 2.5v avdd1x = 3.3v 12538-243 figure 43 . offset error vs. pga gain, low power mode ad7770 data sheet rev. c | page 24 of 97 C18 C16 C14 C12 C10 C8 C6 C4 C2 0 offset error (v) power supply setting temperature = 25c v in = 0v v ref = 2.5v gain = 1 gain = 2 gain = 4 gain = 8 3.0 3.6 3.3 12538-244 figure 44 . offset error vs . power supply setting , high resolution mode C50 40 30 20 10 0 C10 C20 C30 C40 C40 C20 0 20 40 60 80 100 120 offset drift (v) temperature (c) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 avdd1x = 3.3v 12538-245 figure 45 . offset drift vs . temperature C0.043 C0.035 C0.026 C0.017 C0.008 0 0.008 0.017 3.0 3.3 3.6 gain error (%) a vdd1x supp l y (v) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-246 temper a ture = 25c gain = 1 v ref = 2.5v v in = 0dbfs C16 C14 C12 C10 C8 C6 C4 C2 4 2 0 offset error (v) power supply setting temperature = 25c v in = 0v v ref = 2.5v gain = 1 gain = 2 gain = 4 gain = 8 3.0 3.6 3.3 12538-247 figure 47 . offset error vs. power supply setting , low power mode 12538-248 C20 C15 C10 C5 0 5 10 15 20 25 30 45 40 35 0 500 168 1000 gain error drift (ppm) time (hours) 3.0 3.3 3.6 avdd1x supply (v) temperature = 25c gain = 1 v ref = 2.5v v in = 0dbfs gain error (%) C0.043 C0.035 C0.026 C0.017 C0.008 0 0.008 0.017 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-249 figure 49 . gain error vs. avdd1x supply , low power mode data sheet ad7770 rev. c | page 25 of 97 C40 25 105 125 gain error (%) temperature (c) avdd1x = 3.3v v ref = 2.5v v in = 0dbfs C0.400 C0.035 C0.029 C0.023 C0.017 C0.011 C0.005 0 0.005 0.011 0.017 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-250 figure 50 . gain error vs. temperature , high resolution mode 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 1 2 4 8 gain error (%) pga gain high resolution low power temperature = 25c avdd1x = 3.3v v ref = 2.5v v in = 0dbfs 12538-251 figure 51 . channel gain mismatch, high resolution mode C40 25 105 125 tue (% of input) temperature (c) C0.030 C0.025 C0.020 C0.015 C0.010 C0.005 0 0.005 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 temperature = 25c v in = C0.5dbfs v ref = 2.5v avdd1x = 3.3v gain = 1 12538-252 figure 52 . t otal unadusted error (t ue ) vs. temperature , high resolution mode C0.400 C0.035 C0.029 C0.023 C0.017 C0.011 C0.005 0 0.005 0.011 0.017 C40 25 105 125 gain error (%) temperature (c) avdd1x = 3.3v v ref = 2.5v v in = 0dbfs ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-253 figure 53 . gain error vs . temperature , low power mode C40 25 105 125 reference voltage drift (mv) temperature (c) C6 4 3 2 1 0 C1 C2 C3 C4 C5 12538-254 figure 54 . internal reference voltage drift C40 25 105 125 tue (% of input) temperature (c) C0.015 0 C0.005 C0.010 0.005 0.010 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 temperature = 25c v in = C0.5dbfs v ref = 2.5v avdd1x = 3.3v gain = 1 12538-255 figure 55 . total unadusted error (tue) vs. temperature, low power mode ad7770 data sheet rev. c | page 26 of 97 C4 C3 C2 C1 0 1 2 3 4 C2.5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.0 2.5 input current (na) differential input voltage ((ainx+) C (ainxC)) ainx+; v cm = 1.95v ainxC; v cm = 1.95v ainx+; v cm = 1.35v ainxC; v cm = 1.35v v ref = 2.5v avdd1x = 3.3v 12538-256 figure 56 . input current vs. differential input voltage, high resolution mode C40 25 105 125 absolute input current (na) temperature (c) v ref = 2.5v v in = 2.5v avdd1x = 3.3v C12 C10 C8 C6 C4 C2 0 2 4 6 ain0+ ain0C ain2+ ain2C 12538-257 figure 57 . absolute input current vs. temperature, high resolution mode C2.5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.5 2.0 differential input current (na) differential input voltage ((ainx+) C (ainxC)) C5 C4 C3 C2 C1 0 1 2 3 4 5 ainx+ C ainxC; v cm = 1.95v ainx+ C ainxC; v cm = 1.35v v ref = 2.5v avdd1x = 3.3v 12538-258 figure 58 . differential input current vs. differential input voltage , high resolution mode C1.0 C0.8 C0.6 C0.4 C0.2 0 0.2 0.4 0.6 0.8 1.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.0 2.5 input current (na) differential input voltage ((ainx+) C (ainxC)) ainx+; v cm = 1.95v ainxC; v cm = 1.95v ainx+; v cm = 1.35v ainxC; v cm = 1.35v v ref = 2.5v avdd1x = 3.3v 12538-259 figure 59 . input current vs. differential input voltage, low power mode C40 25 105 125 absolute input current (na) temperature (c) v ref = 2.5v v in = 2.5v avdd1x = 3.3v C6 C5 C4 C3 C2 C1 0 1 3 2 4 ain0+ ain0C ain2+ ain2C 12538-260 figure 60 . absolute input current vs. temperature, low power mode C2.5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.5 2.0 differential input current (na) differential input voltage ((ainx+) C (ainxC)) C1 C0.8 C0.6 C0.4 C0.2 0 0.2 0.4 0.6 1.0 0.8 1.2 ainx+ C ainxC; v cm = 1.95v ainx+ C ainxC; v cm = 1.35v v ref = 2.5v avdd1x = 3.3v 12538-261 fig ure 61 . differential input current vs. differential input voltage , low power mode data sheet ad7770 rev. c | page 27 of 97 25 105 125 differential input current (na) temperature (c) v ref = 2.5v v in = 2.5v avdd1x = 3.3v ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-262 figure 62 . differential input current vs. temperature, high resolution mode C140 C120 C100 C80 C60 C40 C20 0 cmrr (db) input frequency (hz) 250.138735 13213.723000 26177.307000 39615.169000 52578.753000 66174.707000 79138.291000 92101.875000 105697.830000 118661.414000 132178.322000 145141.906000 158105.490000 171543.352000 184506.936000 198023.844000 gain = 1 gain = 2 gain = 4 gain = 8 avdd1x = 3.3v v cm = 1.65v + 100mv p-p 12538-263 figure 63 . common - mode reection ratio ( cmrr ) vs . input fre q uency at 16 ksps , high resolution mode C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 ac psrr (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 avdd1x = 3.3v + 100mv p-p temperature = 25c 20014.97 580014.13 1140013.00 1680012.00 2220012.00 2780011.00 3320010.00 3880009.00 4500008.00 5040007.00 5580007.00 6140006.00 6680005.00 7240004.00 7780003.00 8360002.00 8900002.00 9460001.00 12538-264 figure 64 . ac power supply reection ratio (psrr) vs . input fre q uency at 16 ksps , high resolution mode C40 25 105 125 differential input current (na) temperature (c) v ref = 2.5v v in = 2.5v avdd1x = 3.3v 0 1 2 3 4 5 6 7 8 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 12538-265 figure 65 . differential input current vs. temperature, low power mode 171.09249 13450.862 26888.723 40642.77 53922.539 67360.401 811 14.447 94552.309 107990.171 121586.125 135023.987 148461.848 162215.895 175653.757 188933.526 C140 C120 C100 C80 C60 C40 C20 0 cmrr (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 avdd1x = 3.3v v cm = 1.65v + 100mv p-p 12538-266 figure 66 . cmrr vs . input frequency at 4 ksps , low power mode C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 ac psrr (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 avdd1x = 3.3v + 100mv p-p temperature = 25c 20014.97 580014.13 1140013.00 1680012.00 2220012.00 2780011.00 3320010.00 3880009.00 4500008.00 5040007.00 5580007.00 6140006.00 6680005.00 7240004.00 7780003.00 8360002.00 8900002.00 9460001.00 12538-267 figure 67 . ac psrr vs . input f requency at 4 ksps , low power mode ad7770 data sheet rev. c | page 28 of 97 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 attenuation (db) frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 25.0 1943.5 3862.0 5780.5 7699.0 9617.5 11536.0 13454.5 15373.0 17291.5 19210.0 21128.5 23047.0 24965.5 26884.0 28802.5 30721.0 12538-268 figure 68 . filter profiles at 16 ksps, high resolution mode 0 2 4 6 8 10 12 14 16 18 20 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply current (ma) supply voltage (v) all channels enabled avdd1x avdd2x avdd4 iovdd 12538-269 figure 69 . supply current vs. supply voltage, high resolution mode C40 25 105 125 0 25 20 15 10 5 supply current (ma) temperature (c) all channels enabled avdd1x avdd2x avdd4 iovdd 12538-270 figure 70 . supply current vs. temperature, high resolution mode C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 attenuation (db) frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 25.0 503.5 982.0 1460.5 1939.0 2417.5 2896.0 3374.5 3853.0 4331.5 4810.0 5288.5 5767.0 6245.5 6724.0 7202.5 7681.0 12538-271 figure 71 . filter profiles at 4 ksps, low power mode 0 6 5 4 3 2 1 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply current (ma) supply voltage (v) all channels enabled avdd1x avdd2x avdd4 iovdd 12538-272 figure 72 . supply current vs . supply voltage , low power mode C40 25 105 125 0 7 6 5 4 3 2 1 supply current (ma) temperature (c) all channels enabled avdd1x avdd2x avdd4 iovdd 12538-273 figure 73 . supply current vs. temperature, low power mode data sheet ad7770 rev. c | page 29 of 97 C800 C600 C400 C200 0 200 400 600 800 C35.263 C29.594 C22.185 C15.223 C7.366 C0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) ref1C ref1+ ref2C ref2+ 12538-274 figure 74 . reference input current vs. temperature, high resolution mode 0 80 70 60 50 40 30 20 10 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 shutdown supply current (a) supply voltage (v) avdd1x avdd2x avdd4 iovdd 12538-275 figure 75 . shutdown supply current vs. supply voltage 0 40 35 30 25 20 15 10 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 power consumption (mw) supply voltage (v) avdd1x avdd2x avdd4 iovdd only one channel enabled 12538-276 figure 76 . power consumption per channel vs . s upply voltage , high resolution mode C35.263 C29.594 C22.185 C15.223 C7.366 C0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) C600 C500 C400 C300 C200 C100 0 100 200 300 ref1C ref1+ ref2C ref2+ 12538-277 figure 77 . reference input current vs. temperature, low power mode 0 60 50 40 30 20 10 C40 C20 0 20 40 60 80 100 120 shutdown supply current (a) temperature (c) avdd1x avdd2x avdd4 iovdd 12538-278 figure 78 . shutdown supply current vs. temperature 0 14 12 10 8 6 4 2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 power consumption (mw) supply voltage (v) avdd1x avdd2x avdd4 iovdd 12538-279 only one channel enabled ad7770 data sheet rev. c | page 30 of 97 0 90 80 70 60 50 40 30 20 10 power dissipation (mw) avdd1x avdd2x avdd4 iovdd 12538-280 C37.1 C35.9 C28.8 C20.2 C15.2 6.6 27.9 48.1 77.9 104.1 114.5 125.9 temperature (c) figure 80 . power dissipation vs . temperature , high resolution mode power dissipation (mw) avdd1x avdd2x avdd4 iovdd 12538-281 C37.1 C35.9 C28.8 C20.2 C15.2 6.6 27.9 48.1 77.9 104.1 114.5 125.9 temperature (c) 0 5 10 15 20 25 f 81 . p dt . tt l p m C100 C50 0 50 100 150 200 250 300 350 0 44.5 120.3 224.1 327.6 432.3 535.6 639.9 744.8 847.6 950.6 1061.8 1165.5 1268.4 1372.2 1475.0 voltage drift (ppm) elapsed time (hours) 12538-300 figure 82 . internal reference long term drift from 0 hours to 1500 hours data sheet ad7770 rev. c | page 31 of 97 terminology common - mode rejection ratio (cmrr) cmrr is the ratio of the power in the adc output at full - scale frequency, f, to the power of a 100 mv p - p sine wav e applied to the common - mode voltage of ainx+ and ainx ? at frequency, f s . cmrr (db) = 10 log( pf / pf s ) where: pf is the power at frequency, f , in the adc output. pf s is the power at frequency, f s , in the adc output. differential nonlinearity (dnl) error in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. dnl error is often specified in terms of resolution for which no missing codes are guaranteed. integral nonlinearity (inl) error in tegral nonlinearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is a level 1? lsb beyond the last code tr ansition. the deviation is meas ured from the middle of each code to the true straight line. dynamic range dynamic range is the rat io of the rms value of the full - scale input signal to the rms noise measured for an input . the value for dyna mic range is expressed in decibels . channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full - scale frequency sweep sine wave signal to all seven un selected input ch annels and determining how much that signal is attenuated in the se lected channel. the value is given for worst case scenarios across all eight channels of the ad7770 . intermodulation distortion with inputs consisting of sine waves at two frequencies, f a and f b , any active device with nonlinearities creates distortion products at sum and difference frequencies of mf a and nf b , where m, n = 0,1, 2, 3, and so on. intermodulation distortion terms are t hose for which neither m nor n is equal to 0. for example, the second - order terms include (f a + f b ) and ( f a ? fb f b and the third - order terms include (2 f a + f b ), (2 f a ? fb), ( f a + 2 f b ), and ( f a ? 2 f b ). the ad7770 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second - order terms are usually distanced in frequency from the original sine waves, and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - order and third - order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individu al distortio n products to the rms amplitude of the sum of the fundamentals , expressed in decibels. gain error the first transition (from 100 000 to 100 001) occur s at a level ? lsb above nominal negative full scale (? 2.49999 v for the 2.5 v range). th e last transition (from 011 110 to 011 111) occur s for an analog voltage 1? lsb below the nominal full scale ( 2.49999 v for the 2.5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the act ual level of the first transition from the difference between the ideal levels. gain error drift gain error drift is t he ratio of the gain error change due to a temperature change of 1c and the full - scale range (2 n ). it is expressed in parts per million. least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that ca n be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is lsb (v) = n ref v 2 2 lsb ( v in ) = n gain ref pga v 2 2 power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but n ot the linearity of the converter. psrr is the maximum change in the full - scale transition point due to a change in the power supply voltage from the nominal value. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquis t f requency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyqui st frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. offset error offset error is the difference between the ideal mid scale input voltage (0 v) and the actual voltage producing the midscale output code. ad7770 data sheet rev. c | page 32 of 97 offset error drift offset error drift is t he ratio of the offset error change due to a tempera ture change of 1c and the full - scale code range (2 n ). it is expressed in v/c . data sheet ad7770 rev. c | page 33 of 97 theory of operation the ad7770 is an 8 - channel , simultaneo usly sam pling , low noise , 24- bit - adc with integrated digital filtering per channel and src . the ad7770 offers two operation modes: high reso lution mode , which offers up to 32 k sps , and low power mode, which offers up to 8 k sps . the ad7770 employs a - conversion technique to convert the analog input signal into an equivalent digital word. the overview of the - technique is that the m odulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, f clkin . due to the high oversampling rate , this technique spreads the quantization noise from 0 hz to f clkin /2 (in the case of the ad7770 , f clkin rela tes to the external clock); therefore , the noise energy con tained in the band of interest is reduced (see figure 83 ). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see figure 84). the digital filter th at follows the modulator removes the large out of band quantization noise (see figure 85) . f or more information on basic and advanced concepts of - adcs , see the mt - 022 tutori a l and mt - 023 tutor ia l . digital filtering has certain advantages over analog filtering. because digit al filtering occurs after the analog - to - digital conversion process, it can remove noise injected during the conversion. analog filtering cannot remove noise injected during conver sion. quantization noise f clkin /2 band of interest 12538-100 figure 83 . - adc operation, reduction of noise energy c ontained in the band of interest (linear scale x - axis ) f clkin /2 noise shaping band of interest 12538-101 figure 84 . - adc operation, maority of noise energy shifted out of the band of i nterest (linear scale x - axis) f clkin /2 band of interest digital filter cutoff frequency 12538-102 figure 85 . - adc operation , removal of noise energy from the band of interest (linear scale x - axis) the - adc starts the conversions of the input signal after the supplies genera ted by the internal ldos become stable. an external signal is not required to generate the conversions. a nalog inputs the ad7770 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single - ended input signals, as shown in figure 86 through figure 89. table 10 summarizes the maximum differenti al input signal and dynamic range for the different input modes . table 10 . input signal modes input signal mode pga g ain maximum differential signal maximum p eak - to - peak signal true differential all gains ( v ref /pga gain ) 2 v ref / pga gain pseudo differential all gains ( v ref /pga gain ) 2 v ref / pga gain single - ended all gains v ref /pga gain v ref /pga gain ad7770 data sheet rev. c | page 34 of 97 bipolar or unipolar true differentia l a vdd1x C 0.1v ainx+ ainxC a vssx + 0.1v vcm v ref /pga gain 12538-103 figure 86 . - adc input signal configuration , true differential bipolar or unipolar pseudo differentia l a vdd1x C 0.1v ainx+ ainxC a vssx + 0.1v vcm v ref /pga gain 12538-104 figure 87 . - adc input signal configuration , pseudo differential bipolar single-ended ainx+ ainxC a vssx + 0.1v v ref /pga gain 12538-105 figure 88 . - adc input signal configuration, single - ended bipolar v ref /pga gain unipolar single-ended ainx+ ainxC + 0.1v 12538-106 figure 89 . - adc input signal configuration, single - ended unipolar the c ommon - mode input signal is n ot limited, but keep the absolute input signal voltage on any ainx pin between avssx + 100 mv and avdd1x ? 100 mv; otherwise , the input s ignal linearity degrades and , if the signal voltage exceed s the absolute maximum signal rating , damage s the device . figure 90 shows the max imum and minimum voltage common - mode range at different pga gains for a maximum differential input voltage . common-mode vo lt age (v) 1.6500 1.2375 0.8250 0.4125 ( a vdd1x + a vssx)/2 C0.4125 pg a gain 2 4 8 1 C0.8250 C1.2375 C1.6500 true differentia l pseudo differentia l v ref = 2.5v a vdd1x = 1.65v a vssx = C1.65v 12538-107 figure 90 . maximum common - mode voltage ran ge for a maximum differential input signal the ad7770 provides a common - mode voltage pin ( avdd1 x + avss x )/2 ) , vcm, for the single - supply, pseudo differentia l, or true differential input configurations. transfer function the ad7770 can operate with up to a 3.6 v reference, typical at 2.5 v, a n d convert s the differential voltage between the analog inputs (ain x + and ain x ? ) into a digital output. the adc convert s the voltage difference between the analog input pins (ainx+ ? ainx?) into a digital code on the ou tput. the 24 - bit conversion result is in msb first , twos complement format, as shown in table 11 and figure 91 . table 11. output codes and ideal input voltages for pga = 1 condition analog input ( ( ainx+ ) ? ( ainx ? ) ) , v ref = 2.5 v digital output code , twos complement (hex) fs ? 1 lsb +2.499999702 v 0x7fffff midscale + 1 lsb +298 nv 0x000001 midscale 0 v 0x000000 midscale ? 1 lsb ? 298 nv 0xffffff ? fs + 1 lsb ? 2.499999702 v 0x800001 ? fs ? 2.5 v 0x800000 10 0 .. . 0 00 10 0 .. . 0 01 10 0 .. . 0 10 01 1 .. . 1 01 01 1 .. . 1 10 01 1 .. . 1 11 adc code (twos complement) an al og input +fsr C 1.5lsb +fsr C 1lsb Cfsr + 1lsb Cfsr Cfsr + 0.5lsb 12538-108 figure 91 . transfer function data sheet ad7770 rev. c | page 35 of 97 mclk start - ? modulator signal chain for channel x control block pin control control option pin or spi digital filter sinc3 src gain scaling and offset correction conversion data interface mode0 to mode3 cs sclk sdo sdi sync_out sync_in reset drdy doutx sclk format0 and format1 a inx+ pga gain 1, 2, 4, 8 esd protection ainx? spi control 12538-109 figure 92. top level core signal chain core signal chain each - adc channel on the ad7770 has an identical signal path from the analog input pins to the digital output pins. figure 92 shows a top level implementation of this signal chain. prior to each - adc, a pga maps sensor outputs into the adc inputs, providing low input current in dc (8 na in high resolution mode) single-ended input current, and 4 na differential input current in high resolution mode), an 8 pf input capacitance in ac, and configurable gains of 1, 2, 4, and 8. see the an-1392 application note for more information. each adc channel has its own - modulator, which oversamples the analog input and passes the digital representation to the digital filter block. the data is filtered, scaled for gain and offset, and is then output on the data interface. to minimize power consumption, the channels can be individually disabled. capacitive pga each - adc has a dedicated pga, offering gain ranges of 1, 2, 4, and 8. this pga reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the ad7770 . the pga maximize the signal chain dynamic range for small sensor output signals. the ad7770 uses chopping of the pga to minimize offset and offset drift in the input amplifier, reducing the 1/f noise as well. for the ad7770 , the chopping frequency is set to 128 khz for high resolution mode, and 32 khz for low power mode (see the an-1392 application note for more information). the chopping tone is rejected by the sinc3 filter. to minimize intermodulation effects that may cause image in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency. the capacitive pga common-mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within avssx + 100 mv to avdd1x ? 100 mv. see figure 90 for the maximum common-mode voltage at maximum differential input signals. internal reference and reference buffers the ad7770 integrates a 2.5 v, 10 ppm/c typical, voltage reference that is disabled at power-up. the buffered reference is available at pin 49 and offers up to 10 ma of continuous current. a 100 nf capacitor is required if the reference is enabled. in applications where a low noise reference is required, it is recommended to add a low-pass filter (lpf) with a cutoff frequency (f cutoff ) below 10 hz to the ref_out pin. connect the output of this filter to refx+, and connect avssx to refx?. in this scenario, configure the - reference to be external by configuring the reference buffers in enable or precharge mode. an example of performance with and without the output filter is shown in figure 93. 115 105 95 85 75 snr (db) 0.05 0.50 1.00 2.00 2.50 differential input voltage (v) v ref = internal reference f cutoff < 10hz 12538-110 figure 93. snr adding external lpf with v ref = internal reference and f cutoff < 10 hz the ad7770 can be used with an external reference connected between the refx+ and refx? pins. recommended reference voltage sources for the ad7770 include the adr441 and adr4525 family of low noise, high accuracy voltage references. ad7770 data sheet rev. c | page 36 of 97 adc modulator sinc filter data interface control mclk divider high resolution mode: mclk/4 low power mode: mclk/8 dclk divider 1, 2, 4, 8, 16, 32, 64, 128 dec rates = from 64 to 4095.99 mod_mclk dclkx drdy dout3 to dout0 pga ainx+ mclk ainxC 12538-111 figure 94 . clock generation on the ad7770 the reference buffers can be ope rated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer pre - q mode. i n buffer enabled mode , the buffer is fully enable d , minimizing the current requirements from the external references. note that the buf fer output voltage headroom is 100 mv from the rails. in buffer bypassed mode, t he external reference is directly connecte d to the adc reference cap acitor s ; the reference must provide enough current to correctly charge the internal adc reference capacitors . in this mode of operation, a slight de gradation in crosstalk is expected because the adc channels are not isolated from each other . buffer pre - charged (p re - q ) mode is the default operation mode. it is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to pre charge the internal adc reference capacitors . during the final phase of the acquisition , the reference is connected directly to the adc capacitors . this mode has some benefits compared to the buffer enabled and buffer bypassed modes. in buffer pre - q mode, the reference current requirements are minimized compared to buffer bypassed mode and the noise contribution from the internal reference buffers is removed ( compared to buffer enabled mode ) . in buffer pre - q mode , the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the adc reference capacitors . integrated ldo s the ad7770 has three internal ldo s to regulate the internal supplies: two ldos for the analog block and one ldo for the digital core. the internal ldos requires an external 1 f decoupling capacitor on the dregcap, areg1cap, and the areg2cap pins. the ldo slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsi ng the reset pin at power - up is required to guarantee that the digital block initializes correctly . clocking and samplin g the ad7770 includes eight - adc cores. each adc receive s the same master clock signal. the ad7770 requires a maximum external mclk frequency of 8192 khz for high resolution mode and 4096 khz for low power mode . the mclk is internally divided by 4 in high performance mode and by 8 in low p ower mode to produce the modulator mclk ( mod_mclk ) signal used as the modulator sampling clock for the adcs. the mclk can be decreased to accommodate lower odrs if the minimum odr selected by the sinc3 filter is not low enough. if the external clock is low er than 2 56 khz, set the clk_qual_dis bit (in spi control mode only ) . the ad7770 integrates an internal oscillator clock that initialize s the internal register s at power - up. the clk_ sel pin defines the external c lock used after initialization ( see table 12) . table 12 . clock sources clk_ sel state clock source connection 0 cmos input to xtal2/mclk, iovdd logic level. xtal1 must be tie d to dgnd . 1 crystal connected between xtal1 and xtal2 /mclk . the mclk signal generate s the dclk output signal , which in turn clock s the - conversion data from the ad7770 , as shown in figure 94. digital reset and sy nchronization p ins an external pulse in the sync_in pin generates the inte rnal reset of the digital block; this pulse does not affect the data programmed in the internal registers. a pulse in this pin is required in two cases as follows : x after updating one or more register s directly related to the sinc3 filter. these are power mode, offset, gain, and phase compensation . x to s ynchronize m ultiple devices . the pulse in the sync_in pin must be synchronous with mclk. data sheet ad7770 rev. c | page 37 of 97 there are two different ways to achieve a synchronous pulse if the controller/processor cannot generate it, as follows: ? applying an asynchronous pulse on the start pin, which is then internally synchronized with the external mclk clock, and the resulting synchronous signal is output on the sync_out pin. ? triggering the sync_out internally. when the ad7770 is configured in spi control mode, toggling bit 0 in the general_user_config_2 register generates a synchronous pulse that is output on the sync_out pin. the sync_in and sync_out pins must be externally connected if internal synchronization is used. if multiple ad7770 devices must be synchronized, the sync_out pin of one device can be connected to multiple devices. this synchronization method requires the use of a common mclk signal for all the ad7770 devices connected, as shown in figure 95. if the start pin is not used, tie it to iovdd. start sync_in mclk sync_out start sync_in mclk sync_out nc start sync_in mclk sync_out nc ad7770 ad7770 ad7770 synchronization logic asynchronous pulse digital filter synchronization logic iovdd iovdd digital filter synchronization logic digital filter mclk 12538-112 notes 1. nc = no connect. figure 95. multiple ad7770 devices synchronization digital filtering the ad7770 offers a low latency sinc3 filter. most precision - adcs use sinc3 filters because the sinc3 filter offers a low latency path for applications requiring low bandwidth signals, for example, in control loops or where application specific postprocessing is required. the digital filter adds notches at multiples of the sampling frequency. the digital filter implements three main notches, one at the maximum odr (32 khz or 8 khz, depending on the power mode) and another two at the odr frequency selected to stop noise aliasing into the pass band. figure 96 shows the typical filter transfer function for the high resolution and low power modes using a decimation rate of 128. frequency (khz) gain (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 010 30 20 40 60 50 low power mode decimation = 128 high resolution mode decimation = 128 12538-113 figure 96. sinc3 frequency response the sample rate converter featured allows fine tuning of the decimation rate, even for noninteger multiples of the decimation rate. see the src section for more information on filter profiles for noninteger decimation rates. shutdown mode the ad7770 can be placed in shutdown mode by pulling avdd2 to ground and connecting 1 m resistance, pulled low, to xtal2. in this mode, the average current consumption is reduced below 1 ma, as shown in figure 97. ?40 ?0.5 0 0.5 1.0 10 temperature (c) 60 125 i avdd1x i avdd2x i avdd4x i iovdd avddx = 3.3v iovdd = 3.3v supply current (ma) 12538-114 figure 97. shutdown current ad7770 data sheet rev. c | page 38 of 97 controlling the ad7770 the ad7770 can be controlled using either pin control mode or spi co ntrol mode . pin control mode allows the ad7770 to be hardwired to predefined settings that offer a subset of the over all functionality o f the ad7770 . in this mode, the src and diagnostic features or extended errors source are not available. controlling the ad7770 over the spi allows the user access to the full monitoring, diagnostic , and - control functionality. spi control offers additional functional ity such as offset, gain , and phase corre ction per channel , in addition to access to the flexible s rc to achieve a coherent sampling. see table 13 for more details about these different configurations. p in control mode in pin control mode, the ad7770 is configured at power - up based on t he level of the mode pins, mode 0, mode1, mode2 , and mode3. these four pins set the following functions on the ad7770 : the mode of operation, the decimation rate/odr, the pga gain, and the reference source, as shown in table 14. due to the limited number of mode pins and the number of options available, the pga gain control is grouped into blocks of 4, and the odr is selected for the maximum value defined by the decimation rate; odr (khz) = 2048/decimation for high resolution mode, and odr (khz) = 512/decimation for low power mode. depending on the mode selected, the device is configured to use an external or an internal reference. the conversion data can be read back using the spi or the data output interface , as shown in table 13 . if the data output interfac e is used to read back the data f r o m the conversions, t he number of dout x lines enabled and the num ber of clocks required for the - data transfer are deter mined by the logic level of the conv st _sar , format 0 , and format 1 pins . in this case, the dclk2, dclk1 , and dclk0 pins select the - output interface and control the dclk x divide function, which is a submultiple of mclk, as shown in table 15 . the dclk x div ide function sets the frequency of the data output interface dclk x signal. the dclk minimum frequency depends on the decima - tion rate and operation mode. see the data output interface section for more details about the minimum dclk x frequency. all the pins that define the ad7770 configuration mode are re evaluated each time the sync_in pin is pulsed. t he t ypical connection diagram for pin control mode is shown in figure 98. table 13. for mat of the data interface conv st _sar state format 1 format 0 control mode data output mode 1 0 0 pin spi output 0 1 pin spi output 1 1 pin spi output 1 1 spi defined in register 0x014 0 0 0 pin dout0, channel 0 and channel 1 dout1, channel 2 and channel 3 dout2, channel 4 and channel 5 dout3, channel 6 to channel 7 0 1 pin dout0, channel 0 to channel 3 dout1, channel 4 to channel 7 1 0 pin dout0, channel 0 to channel 7 1 1 spi defined in register 0x014 table 14 . pin mode options pin state decimation rate power mode pga gain channel reference source mode3 mode2 mode1 mode0 channel 0 to channel 3 channel 4 to channel 7 0 0 0 0 1024 high resolution 1 1 external 0 0 0 1 512 high resolution 1 1 external 0 0 1 0 256 high resolution 1 1 external 0 0 1 1 128 high resolution 1 1 external 0 1 0 0 64 high resolution 1 1 external 0 1 0 1 512 high resolution 1 4 external 0 1 1 0 256 high resolution 1 4 external 0 1 1 1 128 high resolution 1 4 external 1 0 0 0 64 high resolution 1 4 external data sheet ad7770 rev. c | page 39 of 97 pin state decimation rate power mode pga gain channel reference source mode3 mode2 mode1 mode0 channel 0 to channel 3 channel 4 to channel 7 1 0 0 1 512 high resolution 1 1 internal 1 0 1 0 256 high resolution 1 1 internal 1 0 1 1 128 high resolution 1 1 internal 1 1 0 0 512 low power 1 1 external 1 1 0 1 256 low power 1 1 external 1 1 1 0 128 low power 1 1 external 1 1 1 1 64 low power 1 1 external table 15 . dclk x select ion for pin control mode state dclk2/sclk dclk1/sdi dclk0/sdo mclk divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 adc d at a seria l inter f ace spi contro l inter f ace fpg a or ds p a vdd 3.3v externa l reference a vssx a vssx ain7+ ain7C ain0+ ain0C pg a vcm a vdd1x buffer buffer ad7770 dregca p convst_sar mode3 t o mode0 refx+ refxC ref_out a vdd4 a vssx a vssx a vdd2x a vdd 3.3v a vdd 3.3v iovdd 1.8v t o 3.6v a vssx aregxca p a vssx a vssx iovdd 24-bit - adc sinc3/src sync_in drd y sync_out s t art reset dclk cs sclk sdo clk_se l x t al2 dclk2 t o dclk0 x t al1 dout0 dout1 spi/sport sl a ve inter f ace dout2 dout3 spi master inter f ace pg a vcm sdi form a t1 and form a t0 clock source 12538- 1 15 figure 98 . pin mode connection diagram with external reference ad7770 data sheet rev. c | page 40 of 97 adc dat a seria l inter f ace spi contro l inter f ace fpg a or ds p a vdd 3.3v a vssx a vssx ain7+ ain7C ain0+ ain0C pga vcm a vdd1x buffer ful l buffer buffer ad7770 dregca p convst_sar gpio2 t o gpio0 refx+ refxC ref_out a vdd4 a vssx a vdd2x a vdd 3.3v iovdd 1.8v t o 3.6v a vssx aregxca p a vssx a vssx iovdd auxain+ auxainC 24-bit - adc 12-bit sar adc mux diagnostic inputs sinc3/src sync_in drd y sync_out st art reset dclk cs sclk sdo sdi clk_se l form a t0 xt al2 form a t1 iovdd iovdd xt al1 dout0 dout1 spi/sport sla ve inter f ace dout2 dout3 spi master inter f ace pga vcm clock source 12538- 1 16 figure 99 . spi control mode connection diagram with internal reference spi c ontrol the second option for control and monitoring the ad7770 is via the spi. this option allows access to the full function ality on the ad7770 , including access to the sar converter, phase synchronization, offset and gain a djustment, diagnostics and the src . to use the spi control , set the format0 and format 1 pins to logic high. in this mode, the spi can also read the - conversati on data by setting the spi_slave _ mode_en bit. t he t ypical connection diagram for spi control mode is shown in figure 99. functionality available in spi mode spi control of the ad7770 offers the super set of the functions and di agnostics. the spi control functionality section describes the functionality and diagnostics offered when in spi control mode. offset and gain correction offset and gain registers are available for system calibration. the gain regis ter is preprogrammed during final production for a pga gain of 1, but can be overwritten with a new value if required. the gain register is 24 bits long and is split across three registers , chx_gain_upper_byte, chx_gain_mid_byte, and chx_gain_lower_byte, w hich set the gain on a per channel basis. the gain value is relative to 0x555555, which represents a gain of 1. the offset register is 24 bits long and is spread across three byte registers, chx_offset_upper_byte, chx_offset_mid_ byte, and chx_offset_lower _byte. the default value is 0x000000 at power - up. program the offset as a twos complement , signed 24 - bit number. if the channel gain is set to its nominal value of 0x555555, an lsb of offset register adjustment changes the digital output by ? 4/3 lsbs . as a n example of calibration, the offset measured is ?200 lsb (with both ainx pins connected to the same potential). an offset adjustment of ? 150 lsb change s the digital output by ? 150 (? 4/3) = 200 lsbs (gain value = 0x555555), representing this number as t wo complement, 0xffffff ? 0x96 + 1 = 0xffff70. program the offset register as follows : x chx_offset_upper_byte = 0xff x chx_offset_mid_byte = 0xff x chx_offset_lower_byte = 0x70 note that the offset compensation is performed before the gain compensation. the gain is programmed during final test ing for pga gain = 1. the gain register value s can be overwritten; however , after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting. if the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is 0x555555 0.75 = 0x400000 then, a n lsb of the offset register adjustment changes the digital output by ? 4/3 0.75 = 1 lsb. program the gain register as follows : x chx_gain_upper_byte = 0x40 x ch x_gain_mid_byte = 0x00 x chx_gain_lower_byte = 0x00 data sheet ad7770 rev. c | page 41 of 97 spi control functionality global control functions the following list details the global control functions of the ad7770 : ? high resolution a nd low power modes of operation ? o dr : src ? vcm buffer power - down ? internal/ external reference selection ? enable, pre charged , or bypassed reference buffer modes ? internal r eference power - down ? sar diagnostic mux ? sar power - down ? gpio write/read ? spi sar conversion readback ? spi slave mode read - results ? sdo and dout x drive strength ? dout x mode ? dclk division ? internal ldo bypassed ? crc protection : enable d or disable d per channel functions the following list details the per channel functions of the ad7770 : ? pga gain ? - channel power - down ? phase delay: synchronization phase offset per channel ? calibrati on of offset ? calibration of gain ? - input signal mux ? channel error register ? pga gain phase adjustment the ad7770 phase delay can be adjusted to compensate for phase mismatches between chan nels due to sensors or signal channel phase errors connected to the ad7770 . achieve phase adjustment by programming the chx_sync_offset register. this programming de lays the synchronization signa l by a certain number of modulator clo cks ( mod_clk ) to individually ini tiate the digital filter for each - a dc. in others words, program the channel with a higher phase with p hase 0, whereas for the channel with lower phase, delay to compensate the phase mismatch. the phase adjustment reg ister is read after a pulse on the sync_in pin ; conse que ntly, any further changes on the register have no effect unles s a pulse is generated (see the digital reset and synchronization pins section for more information on how to generate a pulse in the pin). the phase offset register is multiplied internally by a factor (n) that depends on the decimation rate, as shown in table 16. table 16 . phase adjustment vs. decimation rate phase adjustment compensation (n) decimation rate 1 255 2 511 4 1023 8 2047 16 4095 the maximum phase delay cannot be equal to or greater than the decimation rate. if this is the case, the value changes internally to the decimation rate value minus 1. when the chx_sync_offset register is written it automatically overwrites itself multiplied by the corresponding factor (n), as defined in table 12 . as chx_sync_offset is only 8 bits long, the resulting value will be scaled down to fit 8 bits. in order to know whether the phase adjustment has clipped or not, see table 17. table 17. chx_s ync_offset n chx_sync_offset overwrite 255 chx_sync_offset n 511 chx_sync_offset n/2 1023 chx_sync_offset n/4 2047 chx_sync_offset n/8 4095 chx_sync_offset n/16 as an example, the phase mismatch between channel 0 and channel 1 is 5, and the odr is 5 ksps in high resolution mode. in this case, the decimation rat e is 2048 khz/5 khz = 409.6, which means that the offset register value is multiplied internally by 2. a ssuming an input signal of 50 hz, the number of mod_ mclk pulses required to sample a full period is 2048 khz/ 50 hz = 40960 > 360/40960 = 0.00878 . if a 5 delay is required, the number of mod_mclk delays must be 569 (5/0.00878) because the offset register is multiplied by 2; the final offset register value is 409.6/2 ? 569/2, which gives a negative value. in this case, if the offset value programmed to the register is higher than 204 (for example, 210 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 0.00878 = 3.58. pga gain the pga gain can be selected individually by appropriately selecting bits[7:6] in the chx_config register, as shown in table 18. table 18 . pga gain settings via chx_config chx_config , bits [7:6] setting pga gain setting 00 1 01 2 10 4 11 8 ad7770 data sheet rev. c | page 42 of 97 if the - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference decimation the decimation defines the sam pling frequency as follows: ? in high resolution mode, th e sampling frequency = mclk/ (4 decimation) ? in low power mode, the sampling frequency = mclk/ (8 decimation) refer to the src section for more information . gpio x pins if the ad7770 operates in spi control mode, the mode pins operate as gpio x pins, as shown in figure 100 . the gpio x pins can be configured as inputs or outputs in any order. register map gpio0 gpio1 gpio2 12538- 1 17 figure 100 . gpio x pin f unctionality configuration control and read back of the gpio x pins are s et vi a bits [2:0] in the gpio_config register (0 = input, 1 = output) and the gpio_data register. among other uses, the gpio s can control an external mux connected to the auxiliary inputs of the sar adc. use this mux to verify the results on the - adc s. in addition, the gpio x pins can be used to externally trigger a new decimation rate. refer to the src section for more information about this functiona lity. - reference configuration the ad7770 can operate with in ternal or external references. i n addition , for dia gnostic purposes, the analog supply can be used as a reference, as shown in table 19. refx?/refx+ allows t he selection of a voltage reference where the refx+ is lower voltage than refx? pin. table 19. - references setting for adc_mux_config , bits 7:6 channel 0 to channel 3 channel 4 to channel 7 00 ref1+/ ref1? ref2+/ ref2? 01 internal reference internal reference 10 avdd1a/avss1a avdd1b/avss1b 11 ref1?/ ref1+ ref2?/ ref2+ reference buffer operation is described in table 20 . the selected reference and buffer operation mode affect all channels. if the - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference . table 20 . reference buffer operation modes reference buffer operation mode refx+ refx enable d buff er_config_1, bit 4 = 1; buff er_config_2 , bit 7 = 0 buffer_config_1, bi t 3 = 1; buffer_config_2, bit 6 = 0 prec harge d buffer_config_1 , bit 4 = 1; buf fer_config_2, bit 7 = 1 buffer_config_1 , bit 3 = 1; b uffer_config_2, bit 6 = 1 disable d buffer_config_1 , bit 4 = 0 buffer_config_1 , bit 3 = 0 table 21 . additional disable power- down blocks block register notes vcm general_user_config _ 1, bit 5 enable by default reference buffer buffer_config_1 , bits [4:3] prec harge d mode by de f ault internal reference buffer general _user_config _ 1, bit 4 disable by default - channel ch_disable , bits [7:0] all channels enable sar general_user_config _ 1, bit 3 disable by default internal oscillator general_user_config _ 1, bit 2 enable by default data sheet ad7770 rev. c | page 43 of 97 power modes the ad7770 offers different power modes to improve the power efficiency , high resolution and low power mode , which can be controll ed via general_user_config _ 1, bit 6 . to further reduce the power , additional blocks can be disabled independent ly, as described in table 21. if the power mode changes, a pulse on the sync_in pin is required. ldo bypassing the internal ldos can be individually bypassed and an externa l supply can be applied direct ly to the are g1cap, areg2cap, or dregcap pin . table 22 shows the absolute minimum and maximum supplies for these pins, as well as the associated regis ter used to bypass the regulator. table 22 . ldo bypassing ldo buffer_config_2, bits[2:0] 1 supply max (v) min (v) areg1cap 1xx 1.9 1.85 areg2cap x1x 1.9 1.85 dregcap xx1 1.98 1.65 1 x means dont care. digital spi the spi serial interface on the ad7770 consists of four signals: cs , sdi, sclk , and sdo . a typical connection diagram of the spi is shown in figure 101 . dsp/fpg a ad7770 cs sclk sdi sdo 12538- 1 18 figure 101 . spi control interface ad7770 is the spi slave, digital signal processor (dsp)/ f ield programmable gate array (f pga ) is the master the spi operates in mode 0 and mode 3 : cpol = 0, cpha = 0 (mode 0) or cpol = 1, cpha = 1 (mode 3). in pin control mode , the sd o can read back the - resu lts, depending on the level of the conv st _s ar pin , as described in table 13. in spi control mode , the spi transfer s data into the on - chip registers while the sdo pin read s back data from the o n - chip registers or read s the sar or the - conversions results, depending on the selected operation mode. the sdo data source in spi control mode is defined by the general_user_config _ 2 and general_user_ config _ 3 registers, as described in table 23. table 23 . spi operation mode in spi control mode general_user_ config _ 2, bit 5 setting general_user_ config _ 3, bit 4 setting 1 mode 0 0 internal register 0 1 - data conversion 1 x sar conversion 1 x means dont care. in spi control mode, there are four different levels of i/o strength on the sdo pin that can be selected in general_user_ config _ 2 , bits [4:3], as described in table 24. table 24 . sdo strength general_user_config _ 2 , bits [4:3] setting mode 00 nominal 01 strong 10 weak 11 extra strong sclk is the serial clock input for the device. a ll data transfers (on either sdo or sdi) occur with respect to this sclk signal. the spi can operate in multiple s of eight bits. for example, i n spi control mode, if the sdo pin is used to read back the data from the internal register or the sar adc, the data frame is 16 bits wide (crc disable d ), as shown in figure 102 , or 24 bits wide (crc enable d ), as shown in figure 103 . in this case, the controll er can generate one frame of 16 bits or 24 bits (w ith and without the crc enabled ) , or 2 or 3 fram es of 8 bits ( with and without the crc enabled ) . when the sdo pin read s back the data from the - channels, 64 bits must be read back from the controller (i n this case , the contro ller can generate a frame of 64 bits either 2 32 bits, 4 16 bits, or 8 8 bits ) . spi crc checksum protection (spi control mode) the ad7770 has a checksum mode that improve s spi robustness in spi control mode . using the checksum ensures that only valid data is written to a register and allows data read from the device to be validated . the spi crc can be enable d by setting the spi_crc_test_en bit . if an error occurs during a register write, the spi_crc_err is s et in the error register. e nabling the spi_crc_test_en bit results in a crc checksum being performed on all the r/ w operations. when spi_ crc_test_en is enabled, an 8 - bit crc word is appended to every spi transaction for sar and registe r map operations. for more information on - readback operations, see the crc header section. to e nsur e that the register write is successful, it is recommended to read back the register and verify the checksum. for crc checksum calculations, the following polynomial is always used: x 8 + x 2 + x + 1. see the spi control mode checksum section for more information . ad7770 data sheet rev. c | page 44 of 97 spi read/write register mode (spi control mode ) the ad7770 has on - board registers to configure and control the device. the registers have 7 - bit address es the 7 - bit register address on the sdi line select s the register for the read/write function. the 7 - bit register address follows the r/ w bit in the sdi data. the 8 bits on the sdi line following the 7 - bit register address are the data to be written to the selected register if the spi is a write transfer. data on the sdi line is clocked into the ad7770 on the rising edge of sclk, as shown in figure 3 . the data on the sdo line during the spi transfer contain s the 8 - bit 00 10 0000 header: 8 bits of register data in the case of a read (r) operation , or 8 zero s in the case of a write ( w ) operation . with the crc disabled, the basic data frame on the sdi line during the transfer is 16 bits long, as shown in figure 102. when the crc is enabled , a minimum frame length of 24 sclk periods are required on spi transfers. the 24 bits of data on the sdo line c onsist of an 8 - bit header ( 00 10 0000), 8 bits of data , and an 8 - bi t crc ( see figure 103) . r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 0 sdo cs sclk sdi 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 12538- 1 19 figure 102 . 16 - bit spi transfer crc disabled r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 12538-120 figure 103 . 24 - bit spi transfer crc enabled spi sar diagnostic mode (spi control mode) setting bit 5 in the general_user_config _ 2 register configures the sdo line to shift out data from the sar adc conversions, as described in table 23. in sar mode, the ad7770 internal registers can be written to , but any readback command is ignored because the sdo data frame is dedicated to shift out the conversion results from the sar adc. to exit this mode of operation , reset bit 5 in the general_ user_config _ 2 register. the data on the sdo line during the spi transfer contains a 4 - bit 0010 header and the 12- bit sar conversion result if the crc is disabled . when the crc is enabled, a minimum frame length of 24 sclk periods are required on spi trans fers. the 24 bits of data on the sdo line consist of a 4 - bit header (0010), the 12- bit data, and an 8 - bit crc, as shown in figure 104. p er the spi read /write register mode (see the spi read/write register mode section), the sdi line contains the r/ w bit, a 7 - bit register address, the 8 - bit data , and an 8 - bit crc (if enable d ). to avoid unwanted w rites to the internal register while the sar conversions are read back through the sdo line, it is recom - mended to send a readback command, for example, 0x8000, to the device , which is ignored bec a u s e the sdo pin shift s out the content of the sar adc. if consecutive conversion s are performed in the sar adc , read back the result from the previous conversion before a new conversion is generated. o therwise , the results are corrupted. - d ata, adc mode in pin control mode, the spi can be used to read back the - c onversions as described in table 13. in spi control mode, the spi read s back the - con versions by setting general_ user_ config _ 3 , bit 4, as described in table 23 ; in this mode, the ad 7770 inter nal register can be written to , but any readback command is ignore d because the sdo data frame is dedicated to shifting out the conversion results from the - adcs. to avoid unwanted writes to the internal r egister, it is recommended to send a r eadback command, for example, 0x8000 , to the device , which is ignored because the sdo pin shift s out the content of the - adc. the sdo pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 32 bits, 4 16 bits, or 8 8 bits. data sheet ad7770 rev. c | page 45 of 97 spi software reset keeping the sdi pin high during 64 consecutives clocks generate s a software reset. r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 0 1 0 sar 1 1 sar 10 sar 9 sar 8 sar 6 sar 7 sar 5 sar 4 sar 3 sar 2 sar 1 sar 0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 12538-121 figure 104 . sar adc/diagnostic mode crc enabled ad7770 data sheet rev. c | page 46 of 97 rms noise and resolution table 25 through table 27 show the dynamic range (dr), rms noise referred to input (rti), effective number of bits (enob), and effective resolution (er) of the ad7770 for various output data rates and gain settings. the numbers given are for the bipolar input range with an external 2.5 v reference. these numbers are typical and are generated with a di fferential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to note that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise. effecti ve resolution = log 2 ( input range / rms noise ) enob = ( dr ? 1.78)/6 high resolution mode table 25 . dr and rti for high resolution mode decimation rate output data rate (sps) f ? 3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) 64 32,000 8369 103.20 12.10 101.96 6.97 99.20 4.71 95.30 3.82 128 16,000 4818.8 109.43 6.00 108.30 3.39 105.07 2.38 100.71 1.94 256 8000 2511 112.97 4.00 112.38 2.13 110.23 1.39 105.98 1.13 512 4000 1269 116.00 2.80 115.86 1.45 113.68 0.92 109.81 0.7 1024 2000 636.3 119.00 1.98 119.19 1.01 116.75 0.65 113.12 0.51 2048 1000 318.5 123.00 1.38 121.98 0.72 119.79 0.46 115.88 0.35 table 26 . enob and er for high resolution mode decimation rate output data rate (sps) f ? 3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) 64 32, 000 8369 17.14 18.66 16.94 18.45 16.48 18.02 15.83 17.32 128 16, 000 4818.8 18.18 19.67 17.99 19.49 17.45 19.00 16.73 18.30 256 8000 2511 18.76 20.25 18.67 20.16 18.31 19.78 17.6 19.08 512 4000 1269 19.27 20.77 19.24 20.72 18.88 20.38 18.24 16.39 1024 2000 636.3 19.77 21.27 19.8 21.24 19.39 20.89 18.79 20.23 2048 1000 318.5 20.43 21.79 20.26 21.73 19.9 21.39 19.25 20.76 low power mode table 27 . dr and rti for low power mode decimation rate output data rate (sps) f ? 3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) 64 8000 2092.2 102.8 12.5 101.63 7.19 99.35 4.84 93.96 4.15 128 4000 1204.8 108.94 6.45 108.38 3.51 104.7 2.47 100.25 2.12 256 2000 627.75 112.7 4.23 112.01 2.24 109.4 1.49 105.18 1.18 512 1000 317.25 115.83 2.94 115 1.51 112.95 0.99 109.14 0.77 1024 500 159.25 118.97 2.04 118.72 1.05 116.43 0.67 112.47 0.54 table 28. enob and er for low power mode decimation rate output data rate (sps) f ? 3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) 64 8000 2092.2 17.07 18.61 16.88 18.41 16.5 17.98 15.61 17.2 128 4000 1204.8 18.09 19.56 18.00 19.44 17.39 18.95 16.65 18.17 256 2000 627.75 18.72 20.17 18.60 20.09 18.17 19.68 17.47 19.01 512 1000 317.25 19.24 20.70 19.10 20.66 18.76 20.27 18.13 19.62 1024 500 159.25 19.76 21.22 19.72 21.18 19.34 20.84 18.68 20.15 data sheet ad7770 rev. c | page 47 of 97 diagnostics and monitoring self diagnostics err or the ad7770 includes self diagnostic features to guarantee the correct operation. if an error is detected, the alert pin is pulled high to generate an external interruption to the controller. in addition, the header of the - output data contain s a n alert bit that inform s the controller of a chip error (s ee the adc conversion output header and data section). b oth the alert pin and bit ( status header ) are automatically cleared if the error is no longer present. the errors related to the spi do not rec over automatically; read back the appropriate register to clear the error . the alert pin and bit reset in the next spi access after the bit is read back. if an error detector is manually disable d , it d oes not generate an internal error and , consequently , the register map or the alert pin and bit are not triggered. there are different sources of errors, as described in table 29. in pi n control code, it is not possible to check the error source, and some source s of error are not enable d . in spi control mode, check the source of an error by reading the appropriate register bit. the status_reg _ x register bits identify the register that generates an error, as summarized in table 29. table 29 . register error source bit name register source err_loc_gen2 gen_err_reg_2 err_loc_gen1 gen_err_reg_1 err_loc_ch7 ch7_err_reg err_loc_ch6 ch6_err_reg err_loc_ch5 ch5_err_reg err_loc_ch4 ch4_err_reg err_loc_ch3 ch3_err_reg err_loc_ch2 ch2_err_reg err_loc_ch1 ch1_err_reg err_loc_ch0 ch0_err_reg err_loc_sat_ch6_7 ch6_7_sat_err err_loc_sat_ch4_5 ch4_5_sat_err err_loc_sat_ch2_3 ch2_3_sat_err err_loc_sat_ch0_1 ch0_1_sat_err in addition, the status_reg_x registers ha ve a bit that indicates if any internal error bit is set , error . this bit clears if the error is no longer present and the register is read back. the init_complete bit in the status_reg_3 indicates that the dev ice is initialized correctly. this bit is not an error bit but an indicator. general errors mclk switch error (spi control mode) after power - up , the ad7770 initiates a clocking handover sequence to pass clocking control to the extern al oscillator, or the cmos clock. in spi mode, if an error occurs in the handove r , the ext_ mclk_switch_err bit is set in the general error register, gen_e rr _reg _ 2. if ext_mclk_switch_err is set , the device is operating off t he internal oscillato r, and is w aiting for an appropriate external clock. to use a slow external clo ck (<265 khz), set the clk_qual_ dis bit. setting this bit also clears the error bit. if the exter nal clock is between 132 khz and 265 khz, depending on the internal synchronization between the internal oscillator and the external clock, the error may not trigger. however, it is still recommended to set the clk_qual_dis bit. if a slow clock is not in use and the error triggers, a reset is required. res et detection the ad7770 general error register contains a reset_detected bit. this bit is asserted if a reset pulse is applied to the ad7770 and is cleared by reading the general error register. this bit indicates that the power - on reset ( por ) initialized correctly on the device . in addition , this bit can detect an unexpected dev ice reset or glitch on the reset pi n. to re s e t this error signa l in spi control mode, toggle the sync_in pin or read from the g eneral error register, gen_err _reg _ 2. to reset this error signal in pin control mode, toggle the sync_in pin. internal ldo status the ad7770 has three i nternal ldo s to regulate the internal analog an d digital supply rails. the ldo s have internal power supply monitors. internal comparators monitor and flag errors with these supplies after they pass a predetermined limit. the aldo1_psm_err, aldo2_psm_err, and dldo_psm_ err bits indicate either a n ldo malfunction , or, if the ldos are bypassed, an incorrect external supply. the internal analog and digital voltage monitors can be disable d by appropriately selecting the ldo_psm_test_en bits . use t he sar adc t o verify the error. additionally, the levels of the internal monitors can be manually trigger ed to check i f the detector works correctly by appropriately sett ing the ldo_psm_trip_test_en bits . these bit s increase the comparator window threshold above the ldo outputs , forcing the comparator to trigger. rom and m emory map crc if an error is found at power - up during the rom verification, or if the internal memory map is corrupted, the ad7770 generates a n error and sets memmap_crc_err or rom_ crc_ err, depending on the source of the error. the checker can be disable d by clearing the memmap_ c rc_test_en and rom_crc_test_en bits . the device must be reset if any of th ese error s trigger . ad7770 data sheet rev. c | page 48 of 97 - adc errors reference detect ( spi control mode) in spi control mode, the ad7770 includes on - chip circuitry to detect if there is a valid reference for conversions or calibration s. if the voltage between the selected refx+ and refx ? pins goes below 0.7 v, the ad7770 detects that it no longer has a valid reference . chx_err_ref_det ca n be interrogated to identify the affected channel, which clear s the bit r egister if the error is no longer present. the voltage detector can be disable d by clearing the ref_det_test_en bit. use t he - adc diagnostic or the sar adc to verify the error. overvoltage and undervoltage events the ad7770 inclu des on - chip over voltage/under voltage circuitry on each analog input pin. when the voltage on an analog input pin goes above av dd1x + 4 0 mv , the chx_ err_ainx_ov bit is set. the error disappears if the input voltage falls below avdd1x ? 40 mv . if an under voltage event occurs (avssx ? 4 0 m v ) , the chx_ err_ainx_uv bit is set. the error disappears if the input vo l tage increase s to avssx + 4 0 m v . the chx_err_ainm_uv, chx_err_ainm_ov, chx_err_ ainp_uv, and chx_err_ainp_ov bits can be read back to verify the affected channel input, which clear s the bits if the error is no longer present . the overvoltage and under voltage detection can be disable d independently by clearing the ainm_ uv_test_en, ainm_ov_test_en, ainp_uv_test_en , or ainp_ov_test_en bits. the input voltage can be checked independently with the sar adc. modulator saturation the ad7770 includes modulator satur ation detection on each of the - adc s. if 20 consecutive codes for the modulator are either all 1s or 0 s , this condition is flagged as a modulator saturation event. reading the chx_err_mod_sat register clear s the bit if the error correct s itself. modulator saturation detection can be disable d by clearing the mod_sat_test_en bit. note that the modulator input volta ge is attenua ted internally , which means that a modulator output of all 1s or 0s represent s a modulator that is out of bounds and that a reset pulse is required. filter saturation the ad7770 includes digital filte r saturation detection on each - adc channel. this detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. reading the chx_err_ filter_sat bit clears the bit if the error corrects itself. the detection can be disable d by clearing filter_sat_test_ en bit. output saturation an output saturation event can occur wh en gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. the output does not wrap. reading the chx_err_output_sat bit clear s the bit if the error correct s itself. the detection can be disab le d by clearing output_sat_ test_en bit. spi transmission errors (spi control mode) all spi errors clear after reading gen_err_reg_1 , which contains the spi errors. these errors are n o t recover ed auto - matically and , consequently , the alert pin and bit rema in set until the error register is read back, and a new spi frame is generated. crc checksum error if the crc checksum is enable d by setting the spi_crc_ test_en b it, an error bit, spi_crc_err, is raised if the crc message does not match the message computed by the ad7770 internal crc block. if the crc message does not match the internally computed message, the register is not updated. sclk counter if the number of clocks generated by the controller is not a multiple of 8 after cs is pulled high, an error bit, spi_clk_ count_err is raised . the last co mmand multiple of 8 is executed; however , t he sclk counter can be disable d by setting the spi_clk_count_test_en bit. invalid read when attempting to read back an invalid register address , the spi_invalid_ read_err bit is set. the invalid readback address detection can be disable d by setting the s pi_invalid_read_test_en bit. invalid write when attem pting to write to an invalid register address or a read only register , the spi_invalid_write_err bit is set. the invalid write address detection can be disable d by setting the spi_invalid_ write_test_en bit. monitoring using the ad7770 sar adc (spi control mode) the ad7770 contains an on - chip sar adc for chip diagnostics, system diagnostics, or measu rement verification. the sar adc has a 12 - bit resolution . the av dd4 and avs s4 pins operate in complete independence of the - adc supplies and , therefore , can be used for chip diagnostics in systems where functional safety is important. the reference for the sar conversion process i s taken from the sar adc supply voltage (avdd4 / avss4) and , therefore , the sar analog input range is from avss4 to avdd4 . data sheet ad7770 rev. c | page 49 of 97 the sar adc has a maximum throughput rate of 256 ksps. the convst _sar pin initiate s a conversion on the sar adc. the maximum allowable frequency of the convst _sar pin is 256 khz . if consecutive conversion s are performed in t he sar adc , read back the result from the previous conversion before a new conversion is generated. o therwise , the results are corrupted . the sar adc is only available in spi control mode. to read conversion results from the sar adc, set the sar_diag_ mode _en bit. after this bit is set, all data s hift ed out from the sdo pin originates from the sar adc conversion, as sh own in figure 105 . the convst_sar signal can be internally deglitched to avoid false triggers. table 30 . sar synchronization and deglitching convst_deglitch_dis ( register 0x 0 13 , bits [7:6] ) effect on convst_ sar 11 convst_sar goes directly to the sar 10 convst_sar reaches the sar when it is 1 .5 / mclk cycles wide increase t he acquisition time by 1.5 / mclk when the deglitch circuitry is enable d . prior to the sar adc, the ad7770 contains an internal multiplexer. this multiplexer can be configured over the spi to set the inputs to the sar adc to be either int ernal circuit nodes ( in the case of diagnostics ) or to select the external auxain+ and auxain? pins. along with converting external voltages, the sar adc can monito r the internal nodes on the avdd, iovdd , and dgnd pins an d the dldo and analog ldo ( aldo ) o utputs. some voltages are internally attenuated by 6, and the resulting voltage is applied to the sar adc, as shown in table 31 . this attenuation is useful because variations in the power supply voltage can be monitored. the inpu t multipl exer of the sar is controlled by the global_ mux_config register , and the differe nt inputs available are described in table 31. the sar adc also contains an sar driver amplifier, as shown in fig ure 106 . this amplifier settle s the sar inpu t to 12 - bit accuracy within the t 33 time. this driver amplifier help s minimize the kick back from the sar converter to the global diagnostic m ux input circuit nodes. use t he auxiliary inputs, auxain+ and auxain? , to validate the - measurements. while operating in spi control mode , the ad7770 ha s three available gpio x ports controlled via the spi. the gpio x pins can be used to control an external , dual 8:1 multiplexer , which , in turn , sample s the eight - c hannels. use t his diagnostic in applications where functional safety is required. this diagnostic aid s in removing the need for a secondary external adc to validate primary measurements on the - channels. temperature sensor the internal die temperature can be measured with an accuracy of 2c. the d ifferential v oltage base emitter (dv be ) is proportional to the temper ature measured referred to 25c. temperature (c) = mv 2 v 6 . 0 ? table 31 . sar mux inputs sar input positive signal negative signal attenuation 6 0 auxa in+ auxain? no 1 d v be avssx no 2 ref1+ ref1? no 3 ref2+ ref2? no 4 ref_out avssx no 5 vcm avssx no 6 areg1cap avssx yes 7 areg2cap avssx yes 8 dregcap dgnd yes 9 avdd1a avssx yes 10 avdd1b avssx yes 11 avdd2a avssx yes 12 avdd2b avssx yes 13 iovdd dgnd yes 14 avdd4 avssx no 15 dgnd avssx yes 16 dgnd avssx yes 17 dgnd avss x yes 18 avdd4 avssx yes 19 ref1 + avssx no 20 ref2+ avssx no 21 avssx avdd4 yes cs sdi sdo 6(77 (1(5/b86(5b21b5( write t o 085(67(5 write t o 085(67(5 219(56215(68 l 75( 219(56215(68 l 75( 12538-123 figure 105 . configuring the ad7770 to operate the spi to read from the sar adc ad7770 data sheet rev. c | page 50 of 97 sar driver contro l logic fifo on-chi p diagnostics spi auxain+ auxainC a vdd4 a vss4 convst_sar mux deglitch sar adc ref 12538-122 figure 106 . sar adc configuration and control table 32. - diagnostic input voltage recommended voltage reference notes/result 0 floating not applicable not applicable 1 floating not applicable not applicable 2 280 mv differential signal internal/ e xternal pga gain calibration 3 external reference , positive/negative external positive full scale 4 external reference , negative/positive external negative full scale 5 external reference , negative/negative external zero scale 6 internal reference , positive/negative internal positive f ull scale 7 internal reference, negative/positive internal negative full scale 8 internal reference , positive/ positive internal zero scale 9 external reference , positive/positive external zero scale - adc diagnostics (spi control mode) the ad7770 - adc diagnostic functions are accessible through the spi. the internal mux placed before the p ga has different inputs , allowing the user to sel ect a zero - scale , positive full - scale , or negative full - scale input to the - adc, which can be converted to verify the correct operation of the - adc channel. t he diagnostic mux control signals are shared across all the - channels. depending on the diagnostic selected , connect the - adc reference to a different reference source to guarantee that the conversion is within the measurable range. there are tw o different wa ys to enable the diagnostic mux , as follows : x setting the chx_rx bit . this bit enable s the input - mux. the multiplexer inputs are described in table 32. the reference used during the conversions are controlled by the ref_mux_ctrl bits . x setting chx_ref_monitor . this bit has the same effect as enabling the chx_rx bit and select s the vdd1x / avss x supplies as the main reference . if the ainx pin is connected to avssx, the input range is outside the range of avss x + 10 0 mv ; therefore, results may differ slightly from the expected value. alternatively, t he inputs can be used to calibrate gain and of fset errors. data sheet ad7770 rev. c | page 51 of 97 - ? outpu t data adc conversion outpu t header and data the ad7770 - c onversion results are output on the dout0 to dout3 pins or over the spi , depending on the selected interface. if the doutx interface is selected, the ad7770 acts as the master in the transmission. if the spi is selected, the controller is the master. the drdy signal indicates the end of conversion indepen dent of the interface selected to read back the - conversion . when the spi read s back the - conversion, if a new conversion is completed ( drdy falling edge ) before the previous conversion is read back, the results from previous conversion are overwritten and , consequently , the previous conversion data is corrupted. for each channel , the wi d th is 32 bits long: 8 bits for the header and 24 bits for the - c onversion, as shown in figure 107. at a 1 1 76 76 doutx drd y +((51 12538-124 figure 107 . adc output 8- bit header plus 24 - bit conversion data in pin control mode, the header is fixed to the crc while in spi mode, and ca n be selected between crc and error headers. crc header t he crc header is the header generated in pin control mode or in spi mode if dout_header_format is set. as shown in figure 108 , the header consists of a n alert bit, three bits for the adc channel id , as shown in table 33 , and four bits for the crc. the chip error bit is set high if an error is detected in any channe l, as explained in the general errors section. the alert bit remains 1 until the error disappears. alert ch_id_2 ch_id_1 ch_id_0 crc crc crc crc 12538-200 figure 108 . crc header table 33 . channel id channel ch_id_2 ch_id_1 ch_id_0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 the crc generated is eight bit s long; the 4 msbs are placed on the header for the first channel in the pairing and the 4 lsbs on the header of the second channel in the pairing, as shown in table 34. if a channel is disabled, the 24 - bit output data for this channel is 0x000000 . table 34. 8 - bit crc, header configuration (channel 2) alert 0 1 0 crc7 crc6 crc5 crc4 table 35. 8 - bit crc, header configuration (channel 3) alert 0 1 1 crc3 crc2 crc1 crc0 error header (spi control mode) in spi control mode, the default header can be replaced by an er ror header. if the - conversion is read back through the spi , disable the crc by clearing the spi_crc_test_en bit . i f the doutx interface is used , clear the dout_header_ forma t bit. the error header provides information of common error sources specific for each channel , as shown in table 36. modulator and filter errors are indicated even if the checker for th ese error s are specifically disable d, as described in the - adc errors section . table 36 . status header output bit s name description 7 alert this bit is set high if any of the enabled diagnostic functions have detected an error , including an e xternal clock not detected, a memory map bit flip, or an internal crc error. this bit is n ot channel specific . the bit clears if the error is no longer present. [ 6:4 ] ch_id_ [2:0] thes e bits indicate which adc channel the follo wing conversion data came from ( see table 33). 3 reset_detected this bit indicates if a reset condition occurs . this bit is not channel specific . 2 modulator_ saturate this bit i ndicates that the modulator output is 20 consecutive 0s or 1 s . the bit reset s automatically after the error is no longer present. 1 filter_ sa turate this bit indicates that the filter output is out of bounds. the bit reset s automatically after the error is no longer present. 0 ain_ov_uverror this bit indicates that there is an ainx over voltage/under voltage condition on the inputs . this bit is set until the appropriate register is read back and the error is no longer present. ad7770 data sheet rev. c | page 52 of 97 src (spi c o ntrol m o de) the ad7770 impleme nts a feature cal led the src on each - channe l that allows the user to configure the output data rate or sampling frequency to any desired value , including non integer values. the src achieves fine resolution control over the - adc odr . in applications where the odr must change based on changes in the input signal to maintain sampling coherency , the src provide s fine control over the odr. for example , to achieve the highest classific ation standard, class a, in power quality applications, coherency must be maintained for 0.01 hz changes in the input power line. use t he src to achieve this sampling frequency accuracy. in pin control mode, the decimation rate is fixed per the predefined pin control options. c onsequently , a noninteger number cannot be selected, as shown in table 13. to set the odr , the user must program up to four registers , depe nding on the decimation value: two registers to program the integer value , n ( the effective decimation rate) , and two registe r s to program the decimal value, the interpolation factor (if ). th e integer value registers are s r c _n_msb , bits [3:0] and s r c _n_lsb , bits [7:0]. the dec imal part value registers are s r c _if_msb , bits [7:0] and s r c _if_lsb , bits [7:0]. as an example, if an output data rate of 2.8 kh z is required, the decimation rate equates to ? high resolution mode = 2048 / 2.8 = 731.428 ? low power mode = 512/ 2.8 = 182.857 the register values for high resolution mode are as follows: ? 731 ( d ecimal ) = 0x2db ? s r c _n_msb , bits [3:0] = 0x02 ? s r c _n_lsb , bits [7:0] = 0xdb ? 0.428 (decimal) = 0.428 2 16 = 28049 (decimal) = 0x6d91 ? s r c _if_msb , bits [7:0] = 0x6d ? s r c _if_lsb , bits [7:0] = 0x91 the src resolution depends on the decimal number used in the decimation, as well as the modulator clock (mod_clk), as follows: 16 2 16 2 1 2 3 2 + + = dec dec mod resolution mclk here mod mclk is the modulator frequency. dec is the decimal p ortion of the decimation rate. in high resolution mode, for a decimal decimation of 450, the resolution is defined as sps 10 4 . 15 2 1 450 3 450 2 2048 6 C 16 2 2 16 = + gpio2 gpio0 gpio0 gpio0 mclk gpio1 gpio2 mclk gpio1 nc gpio2 mclk gpio1 nc ad7770 ad7770 ad7770 61+521721 logic pulse 7//7(5 61+521721 logic 7//7(5 61+521721 logic 7//7(5 mclk 12538-125 notes 1 12211(7 figure 109 . hardware odr update data sheet ad7770 rev. c | page 53 of 97 src bandwidth the sinc 3 filter architecture allows the user to select a non integer value as the decimation range this versatility means that the filter notches must be adjusted dynamically: two notches at the variable frequency, and one fixed notch to remove the pga chopping tone. consequently , the traditional formula for ?0.1 db and ?3 db bandwidth must be adjusted depending on the selected decimation rate. the bandwidt h transfer function is not linear but can be approximated by using a linear function. figure 110 and figure 111 show the correction factor for the ? 0.1 db and ?3 db bandwidth , respectively , in high resolution . in low power mode , the offset must be divided by 4. for example, when the odr = 1000 sps in l ow power mode, the ? 0.1 db point is hz 71 4 36 . 47 1000 0481 . 0 + = bw 0 200 400 600 800 1000 1200 1400 1600 g5(48(1 y + 25n+ 12538-126 0.1 5.1 10.1 15.1 20.1 25.1 30.1 figure 110 . ? 0.1 db correction factor 9 g5(48(1 y n+ 1 2 3 4 5 6 7 8 25n+ 0 12538-127 0.1 5.1 10.1 15.1 20.1 25.1 30.1 f 111 . 3 b ct ft src group delay and latency the src group delay depends on the selected odr and the power mode, and is defined by the following equation: group delay = odr n src n src pm + _ _ where: pm is a value that depends on the power mode, either 64 for high resolution mode or 32 for low power mode. src_n is the integer value of the programmed odr. odr is the programmed output data rate. the latency is the contribution of the group delay and the calibration time. latency = group d elay + t cal where t cal = 62 t mclk , with a maximum error of 2 t mclk , in high resolution mode; or 121 t mclk , with a maximum error of 4 t mclk , in low power mode. t mclk is the modulator period, mclk/4 in high resolution mode and mclk/8 in low power mode. settling time the settling time is defined by the contribution of all the internal stages, the f ilter delay, and the block calibration. the filter delay is defined as 3/odr. in some extreme cases, as when an external pulse is applied, this value may increase to 4/odr. data output interfac e the - output data interface is defined by the conv st _sar , format0 , and format1 pins in pin control mode at power - up. the format x pins cannot be changed dyna mically. table 14 sho ws the available options for pin control mode. if the device is configured in spi control mode, the spi_slave_mode_ en bit enable s the spi to transmit the - adc conversion results, as s hown in table 23. dout3 to dout0 data interface stand alone mode in standalone mode , the ad7770 interfa ce acts as a master. there are three different dout x configurations, configurable through the format x pins in pin control mode, as shown in figur e 112 through figure 114 , or via the dout_format bits , bits [7:6] , in spi control mode, as described in table 37. figure 115, figure 116 , and figure 117 s how the expected data outputs for different dout x output modes. ad7770 data sheet rev. c | page 54 of 97 table 37. dout x channels dout _format bits /formatx pins number of dout x lines enabled associated channels 00 4 dout0 channel 0 and channel 1 dout1 channel 2 and channel 3 dout2 channel 4 and channel 5 dout3 channel 6 and channel 7 01 2 dout0 channel 0, channel 1, channel 2, and channel 3 dout1 channel 4, channel 5, channel 6, and channel 7 10 or 11 1 dout0 channel 0, channel 1, channel 2, channel 3, channel 4, channel 5, channel 6, and channel 7 dout0 dout1 dout2 dout3 dclk drd y form a t1 dais y -chaining is not possible in this form a t form a t0 ad7770 dgnd dout0: ch 0, ch 1 dout1: ch 2, ch 3 dout2: ch 4, ch 5 dout3: ch 6, ch 7 0 0 00 12538-128 figure 112 . formatx pin configuration format0 = 0, format1 = 0 dout0 dout1 dclk drd y form a t1 iovdd dais y -chaining is possible in this form a t dgnd form a t0 ch 0, ch 1, ch 2, ch 3 output on dout0 ch 4, ch 5, ch 6, ch 7 output on dout1 01 1 0 ad7770 12538-129 figure 113 . formatx pin configuration format0 = 1, format1 = 0 dout0 dclk drd y form a t1 iovdd dais y -chaining is possible in this form a t dgnd form a t0 ch 0 t o ch 7 output on dout0 10 0 1 ad7770 12538-130 figure 114 . formatx pin configuration format0 = 0, format1 = 1 data sheet ad7770 rev. c | page 55 of 97 ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 dclk drd y dout0 sample n sample n + 1 dout1 ch4-s0 ch5-s0 ch6-s0 ch7-s0 ch4-s1 ch5-s1 ch6-s1 ch7-s1 dout0 dout1 12538-131 figure 115 . format 0 = 0, format1 = 0 each dout x outputs two adc conversions (s0 means sample 0 and s 1 means sample 1) ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch7-s0 ch4-s0 ch5-s0 ch6-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 ch7-s1 ch4-s1 ch5-s1 ch6-s1 dclk drd y dout0 sample n sample n + 1 dout1 dout3 dout2 12538-132 figure 116 . format0 = 0, format1 = 1 channel 0 to channel 3 share dout0, and channel 4 to channel 7 share dout1 (s0 means sample 0 and s1 means sample 1) dclk drd y dout0 sample n sample n + 1 sample n + 2 dout3 dout2 dout1 ch0-s0 ch1-s0 ch2-s0 ch...-s0 ch6-s0 ch7-s0 ch0-s1 ch0-s2 ch0-s3 ch1-s1 ch2-s1 ch...-s1 ch6-s1 ch7-s2 ch1-s2 ch2-s2 ch...-s2 ch6-s2 ch7-s2 12538-133 figure 117 . format0 = 1, format1 = 0 channel 0 to channel 7 output on dout0 only (s0 means sample 0 and s1 means sample 1) ad7770 data sheet rev. c | page 56 of 97 daisy - chain mode daisy - chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple adcs from separate ad7770 devices. in daisy - chain configura - tion , only one device has a direct connection between the dout x interface and the digital host. for the ad7770 , daisy - chain capability is implemented by cascading dout0 and dout1 through a number of d evices, or by just using dout0 ( th e number of dout x pins available depends on the selected dout x mode ) . the ability to daisy - chain devices and the limit on the number of devices that can be handled by the chain is dependent on the selected dout x mode and t he decimation rate employed. when operating in daisy - chain mode, it is required that all ad7770 devices in the ch ain are correctly synchronized. see the digital reset and synchronization pins section for more information. this feature is especially useful for reducing the componen t count and wiring connections in , for example, isolated multi converter applications or for systems with a limited interfacing capacity. for daisy - chain operation, there are two different configurations possible , as described in table 38 . using the formatx = 10 mode , dout2 act s as an input pin , as shown in figure 118 . in this case, the dout0 pin of the ad7770 devices is cascaded to the d out2 pin of the next device in the chain. data readback is analogous to clocking a shift register where data is clocked on the rising edge of dclk. table 38. dout x modes in daisy - chain operation dout_format bits / formatx pins number of doutx lines enabled associated channels 01 2 dout0 channel 0 to channel 3 and dout2 dout1 channel 4 to channel 7 and dout3 dout2 input channel dout3 input channel 10 1 dout0 channel 0 to channel 7 and dout2 dout2 i nput c hannel u2 s0 ch0 t o ch7 u2 s0 ch0 t o ch7 u1 s0 ch0 t o ch7 0 0 u2 s0 ch0 t o ch7 u1 s0 ch0 t o ch7 0 u2 s1 ch0 t o ch7 u2 s1 ch0 t o ch7 u1 s1 ch0 t o ch7 0 0 u2 s1 ch0 t o ch7 u2 s3 ch0 t o ch7 0 u2 s0 ch0 t o ch7 u2 s0 ch0 t o ch7 u1 s1 ch0 t o ch7 0 u2 dout0 u1 dout2/din0 u1 dout0 u2 dout2/din0 drd y dclk u2 dout2/din0 dout0 u2 dout2/din0 dout0 12538-134 figure 118 . daisy - c hain co nnection mode, format0 = 1 , format1 = 0 (s0 means sample 0 and s1 means sample 1) ; when connected in daisy - chain mode , dout2 acts as an input pin, represented by din0 data sheet ad7770 rev. c | page 57 of 97 minimum dclk x frequency select the dclkx frequency ratio in such a way that the data is completely shifted out before a new conversion is completed ; otherwise the previous conversion is overwritten and the transmis - sion beco mes corrupt. the minimum dclkx frequency ratio is defined by the decimation rate , the operation mode , and the lines enabled on the dout3 to dout0 data interface s as described in the following equation s. in standa lone mode and h igh r esolution m od e, dclk min_ ratio < decimation /(8 channels_per_dout ) in standalone mode and low power mode, dclk min_ratio < decimation /(4 channels_per_dout ) in daisy - chain mode and high resolution mode, dclk min _ratio < decimation /(8 devices doutx channels ) in daisy - chain mode and low power mode, dclk min_ratio < decimation /(4 devices doutx channels ) as an example, when operating in master interface mode, formatx = 01, the dout0 and dout1 p ins s hift out four - c hannels each and , assuming a maximum output rate in high resolution mode, the decimation = 128. dclk min < 128/ ( 8 4 ) = 4 if the dclk min_ratio is selected above the necessary minimum, a logic 0 is continuously transmitted until a new sample is available. an example in daisy - chain mode , assuming formatx = 01, and with t hree devices connected and a decimation rate of 256 in high resolution mode , is as follows: dclk min_ratio < 256/( 8 3 4 ) = 2.66 = 2 the different ratios are summarized in table 39. table 39. available dclk ratios dclk_clk_div (spi control mode), dclkx (pin control mode) dclk x ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 there are maximum achievable odrs and minimum dclk x frequencies required for a given dout x pin configuration , as shown in table 40 and table 41 . table 40 . maximum odrs and minimum dclk x frequencie s in high resolution mode decimation rate odr (ksps) minimum dclk x (khz) 1 dout x 2 dout x 4 dout x 4095 0.500122 128 64 32 2048 1 256 128 64 1024 2 512 256 128 512 4 1024 512 256 256 8 2048 1024 512 128 16 4096 2048 1024 64 32 8192 4096 2048 table 41 . maximum odrs and minimum dclk x frequencies in low power mode decimation rate odr (ksps) minimum dclk x (khz) 1 doutx 2 doutx 4 doutx 2048 0.25 64 32 16 1024 0.5 128 64 32 512 1 256 128 64 256 2 512 256 128 128 4 1024 512 256 64 8 2048 1024 512 if the ad7770 operates in spi control mode, it is possible to adjust the doutx strength, which can be selected in the dout_drive_str bits, as des cribed in table 42. table 42 . doutx strength dout_drive_str mode 00 nominal 01 strong 10 weak 11 extra strong spi the spi gives the user flexibility to read the conversion from the - adc where the processor or micro controller is the master. when a new conversion is completed, the drdy signal is toggled to indicate that data can be accessed. when drdy t oggles, the internal channel counter is reset and the next spi read originates from channel 0 again. conversely, after the last channel data is read , all successive reads before the next drdy signal originate from ch annel 7 ( lsb ). ad7770 data sheet rev. c | page 58 of 97 cs sdo 12538-135 figure 119 . spi readback, 16 bits per frame cs sdo 12538-136 figure 120 . spi readback, 24 bits per frame the spi operates in multiples of 8 bits per frame; figure 119 shows a readback example in 16 bits per frames, and figure 120 shows a readba c k in 24 bits per frame. note that i f the device is configured in spi control mode, the ad7770 generate s a software reset if the sdi pin is sample d high for 64 consecutive clocks. to avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which genera tes a readback command that is ignored by the device, as explained in the - data, adc mode section . calculating the crc check s um the ad7770 implements two different crc checksum generators, one for the - results and another for the spi control mode. the ad7770 uses a crc polynom ial to calculate the crc checks um value. the 8 - bit crc polynomial used is x 8 + x 2 + x + 1. to replicate the poly nomial division in hardware, remember that the data is left shifted by eight bits to create a number ending in eight logic 0s. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data. an exclusive or (xor ) function is appl ied to the data to produce a new, shorter number. the polynomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process is repeated until the original data is reduced to a value l ess than the polynomial , the 8 - bit checksum. note that the ad7770 crc block preset the input shift registers to 1, meaning that the 8 ms bs of user data must be inverted before compute the algorithm. a n example of the crc ca lculation for 12 - bit data is shown in table 43. table 43 . example crc calculation for 12 - bit data 1 data 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 process data 1 1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 polynomial 1 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 crc 0 1 0 0 0 1 0 0 1 this table represents the division of the data; blank cells are for formatting purposes. data sheet ad7770 rev. c | page 59 of 97 - crc checksum the crc message is calculated internally by the ad7770 on adc pairs. the crc is calculated using t he adc output data from two adc s and bits[ 7:4 ] from the header. therefore, 56 bit s are used to calculate the 8 - bit crc. this crc is split between the two channel headers. the crc data cover s channel pairings as follows : channel 0 and channel 1, channel 2 and channel 3, channel 4 and channel 5, channel 6 , and channel 7. to generate the checksum, the data is left shifted by eight bits to create a number ending in eight logic 1s. the crc is calculated from 56 bits across two consecutive/ channel pairings (channel 0 and ch annel 1, channel 2 and channel 3, channel 4 and channel 5, channel 6 , and channel 7) . the 56 bits consist of the alert bit , the 3 bits for the first adc pairing channel , and the 24 bits of data of each pairing channel. for example , for the second channel pairing, channel 2 and channel 3 , 56 bits = a lert bit + 3 adc channel bits (010) + 24 data bit s (channel 2 ) + alert bit + 3 adc channel bits (011) + 24 data bits (channel 3) spi control mode checksum the crc message is calculated internally by the ad7770 . the dat a transferred to the ad7770 uses the r /w bit, a 7 - bit address , and 8 bits of data for the crc calculation. the crc calculated and appended to the data that it is shifted out uses the previous transmitted r/ w bit, the 7 - bit register add ress , and the 8 - bit data from the readback register. if the previo us com mand was a write command, the 8 bits of data are 0s . if the sar adc is read back, the crc algorithm uses a 0000b header and the 12 bits of sar conversion data. ad7770 data sheet rev. c | page 60 of 97 register summary table 44. register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x000 ch0_config [7:0] ch0_gain ch0_ref_ monitor ch0_rx reserved 0x00 r /w 0x001 ch1_config [7:0] ch1_gain ch1_ref_ monitor ch1_rx reserved 0x00 r/w 0x002 ch2_config [7:0] ch2_gain ch2_ref_ monitor ch2_rx reserved 0x00 r/w 0x003 ch3_config [7:0] ch3_gain ch3_ref_ monitor ch3_rx reserved 0x00 r/w 0x004 ch4_config [7:0] ch4_gain ch4_ref_ monitor ch4_rx reserved 0x00 r/w 0x005 ch5_config [7:0] ch5_gain ch5_ref_ monitor ch5_rx reserved 0x00 r/w 0x006 ch6_config [7:0] ch6_gain ch6_ref_ monitor ch6_rx reserved 0x00 r/w 0x007 ch7_config [7:0] ch7_gain ch7_ref_ monitor ch7_rx reserved 0x00 r/w 0x008 ch_disable [7:0] ch7_ disable ch6_ disable ch5_disable ch4_disable ch3_ disable ch2_ disable ch1_ disable ch0_ disable 0x00 r/w 0x009 ch0_sync_ offset [7:0] ch0_sync_offset 0x00 r/w 0x00a ch1_sync_ offset [7:0] ch1_sync_offset 0x00 r/w 0x00b ch2_sync_ offset [7:0] ch2_sync_offset 0x00 r/w 0x00c ch3_sync_ offset [7:0] ch3_sync_offset 0x00 r/w 0x00d ch4_sync_ offset [7:0] ch4_sync_offset 0x00 r/w 0x00e ch5_sync_ offset [7:0] ch5_sync_offset 0x00 r/w 0x00f ch6_sync_ offset [7:0] ch6_sync_offset 0x00 r/w 0x010 ch7_sync_ offset [7:0] ch7_sync_offset 0x00 r/w 0x011 general_ user_config_1 [7:0] all_ ch_dis_ mclk_en power mo de pdb_vcm pdb_ refout_buf pdb_ sar pdb_ rc_osc soft_reset 0x24 r/w 0x012 general_ user_config_2 [7:0] reserved sar_diag_ mode_en sdo_drive_str dout_drive_str spi_sync 0x09 r/w 0x013 general_ user_config_3 [7:0] convst_ deglitch_dis reserved spi_slave_ mode_en reserved clk_qual_ dis 0x80 r/w 0x014 dout_ format [7:0] dout_format dout_ header_ format reserved dclk_clk_div reserved 0x20 r/w 0x015 adc_mux_ config [7:0] ref_mux_ctrl mtr_mux_ctrl reserved 0x00 r/w 0x016 global_mux_ config [7:0] global_mux_ctrl reserved 0x00 r/w 0x017 gpio_config [7:0] reserved gpio_op_en 0x00 r/w 0x018 gpio_data [7:0] reserved gpio_read_data gpio_write_data 0x00 r/w 0x019 buffer_ config_1 [7:0] reserved ref_buf_ pos_en ref_ buf_ neg_en reserved 0x38 r/w 0x01a buffer_ config_2 [7:0] ref - bufp_ preq ref - bufn_ preq reserved p db_ aldo1_ ovrdrv pdb_ aldo2_ ovrdrv pdb_ dldo_ ovrdrv 0xc0 r/w 0x01c ch0_offset_ upper_byte [7:0] ch0_offset_all[23:16] 0x00 r/w 0x01d ch0_offset_ mid_byte [7:0] ch0_offset_all[15:8] 0x00 r/w 0x01e ch0_offset_ lower_byte [7:0] ch0_offset_all[7:0] 0x00 r/w data sheet ad7770 rev. c | page 61 of 97 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x01f ch0_gain_ upper_byte [7:0] ch0_gain_ all[23:16] 0x00 r/w 0x020 ch0_gain_ mid_byte [7:0] ch0_gain _ all[15:8] 0x00 r/w 0x021 ch0_gain_ lower_byte [7:0] ch0_gain _ all[7:0] 0x00 r/w 0x022 ch1_offset_ upper_byte [7:0] ch1_offset_all[23:16] 0x00 r/w 0x023 ch1_offset_ mid_byte [7:0] ch1_offset_all[15:8] 0x00 r/w 0x024 ch1_offset_ lower_byte [7:0] ch1_offset_all[7:0] 0x00 r/w 0x025 ch1_gain_ upper_byte [7:0] ch1_gain _ all[23:16] 0x00 r/w 0x026 ch1_gain_ mid_byte [7:0] ch1_gain _ all[15:8] 0x00 r/w 0x027 ch1_gain_ lower_byte [7:0] ch1_gain _ all[7:0] 0x00 r/w 0x028 ch2_offset_ upper_byte [7:0] ch2_offset_all[23:16] 0x00 r/w 0x029 ch2_offset_ mid_byte [7:0] ch2_offset_all[15:8] 0x00 r/w 0x02a ch2_offset_ lower_byte [7:0] ch2_offset_all[7:0] 0x00 r/w 0x02b ch2_gain_ upper_byte [7:0] ch2_gain _ all[23:16] 0x00 r/w 0x02c ch2_gain_ mid_byte [7:0] ch2_gain _ all[15:8] 0x00 r/w 0x02d ch2_gain_ lower_byte [7:0] ch2_gain _ all[7:0] 0x00 r/w 0x02e ch3_offset_ upper_byte [7:0] ch3_offset_all[23:16] 0x00 r/w 0x02f ch3_offset_ mid_byte [7:0] ch3_offset_all[15:8] 0x00 r/w 0x030 ch3_offset_ lower_byte [7:0] ch3_offset_all[7:0] 0x00 r/w 0x031 ch3_gain_ upper_byte [7:0] ch3_gain _ all[23:16] 0x00 r/w 0x032 ch3_gain_ mid_byte [7:0] ch3_gain _ all[15:8] 0x00 r/w 0x033 ch3_gain_ lower_byte [7:0] ch3_gain _ all[7:0] 0x00 r/w 0x034 ch4_offset_ upper_byte [7:0] ch4_offset_all[23:16] 0x00 r/w 0x035 ch4_offset_ mid_byte [7:0] ch4_offset_all[15:8] 0x00 r/w 0x036 ch4_offset_ lower_byte [7:0] ch4_offset_all[7:0] 0x00 r/w 0x037 ch4_gain_ upper_byte [7:0] ch4_gain _ all[23:16] 0x00 r/w 0x038 ch4_gain_ mid_byte [7:0] ch4_gain _ all[15:8] 0x00 r/w 0x039 ch4_gain_ lower_byte [7:0] ch4_gain _ all[7:0] 0x00 r/w 0x03a ch5_offset_ upper_byte [7:0] ch5_offset_all[23:16] 0x00 r/w 0x03b ch5_offset_ mid_byte [7:0] ch5_offset_all[15:8] 0x00 r/w 0x03c ch5_offset_ lower_byte [7:0] ch5_offset_all[7:0] 0x00 r/w 0x03d ch5_gain_ upper_byte [7:0] ch5_gain _ all[23:16] 0x00 r/w 0x03e ch5_gain_ mid_byte [7:0] ch5_gain _ all[15:8] 0x00 r/w 0x03f ch5_gain_ lower_byte [7:0] ch5_gain _ all[7:0] 0x00 r/w ad7770 data sheet rev. c | page 62 of 97 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x040 ch6_offset_ upper_byte [7:0] ch6_offset_all[23:16] 0x00 r/w 0x041 ch6_offset_ mid_byte [7:0] ch6_offset_all[15:8] 0x00 r/w 0x042 ch6_offset_ lower_byte [7:0] ch6_offset_all[7:0] 0x00 r/w 0x043 ch6_gain_ upper_byte [7:0] ch6_gain _ all[23:16] 0x00 r/w 0x044 ch6_gain_ mid_byte [7:0] ch6_gain _ all[15:8] 0x00 r/w 0x045 ch6_gain_ lower_byte [7:0] ch6_gain _ all[7:0] 0x00 r/w 0x046 ch7_offset_ upper_byte [7:0] ch7_offset_all[23:16] 0x00 r/w 0x047 ch7_offset_ mid_byte [7:0] ch7_offset_all[15:8] 0x00 r/w 0x048 ch7_offset_ lower_byte [7:0] ch7_offset_all[7:0] 0x00 r/w 0x049 ch7_gain_ upper_byte [7:0] ch7_gain _ all[23:16] 0x00 r/w 0x04a ch7_gain_ mid_byte [7:0] ch7_gain _ all[15:8] 0x00 r/w 0x04b ch7_gain_ lower_byte [7:0] ch7_gain _ all[7:0] 0x00 r/w 0x04c ch0_err_reg [7:0] reserved ch0_err_ ainm_uv ch0_err_ ainm_ov ch0_err_ ainp_uv ch0_err_ ainp_ov ch0_err_ ref_det 0x00 r 0x04d ch1_err_reg [7:0] reserved ch1_err_ ainm_uv ch1_err_ ainm_ov ch1_err_ ainp_uv ch1_err_ ainp_ov ch1_err_ ref_det 0x00 r 0x04e ch2_err_reg [7:0] reserved ch2_err_ ainm_uv ch2_err_ ainm_ov ch2_err_ ainp_uv ch2_err_ ainp_ov ch2_err_ ref_det 0x00 r 0x04f ch3_err_reg [7:0] reserved ch3_err_ ainm_uv ch3_err_ ainm_ov ch3_err_ ainp_uv ch3_err_ ainp_ov ch3_err_ ref_det 0x00 r 0x050 ch4_err_reg [7:0] reserved ch4_err_ ainm_uv ch4_err_ ainm_ov ch4_err_ ainp_uv ch4_err_ ainp_ov ch4_err_ ref_det 0x00 r 0x051 ch5_err_reg [7:0] reserved ch5_err_ ainm_uv ch5_err_ ainm_ov ch5_err_ ainp_uv ch5_err_ ainp_ov ch5_err_ ref_det 0x00 r 0x052 ch6_err_reg [7:0] reserved ch6_err_ ainm_uv ch6_err_ ainm_ov ch6_err_ ainp_uv ch6_err_ ainp_ov ch6_err_ ref_det 0x00 r 0x053 ch7_err_reg [7:0] reserved ch7_err_ ainm_uv ch7_err_ ainm_ov ch7_err_ ainp_uv ch7_err_ ainp_ov ch7_err_ ref_det 0x00 r 0x054 ch0_1_sat_ err [7:0] reserved ch1_err_ mod_sat ch1_err_ filter_sat ch1_err_ output_ sat ch0_err_ mod_sat ch0_err_ filter_sat ch0_err_ output_ sat 0x00 r 0x055 ch2_3_sat_ err [7:0] reserved ch3_err_ mod_sat ch3_err_ filter_sat ch3_err_ output_ sat ch2_err_ mod_sat ch2_err_ filter_sat ch2_err_ output_ sat 0x00 r 0x056 ch4_5_sat_ err [7:0] reserved ch5_err_ mod_sat ch5_err_ filter_sat ch5_err_ output_ sat ch4_err_ mod_sat ch4_err_ filter_sat ch4_err_ output_ sat 0x00 r 0x057 ch6_7_sat_ err [7:0] reserved ch7_err_ mod_sat ch7_err_ filter_sat ch7_err_ output_ sat ch6_err_ mod_sat ch6_err_ filter_sat ch6_err_ output_ sat 0x00 r 0x058 chx_err_ reg_en [7:0] output_ sat_test_ en filter_ sat_test_ en mod_sat_ test_en ainm_uv_ test_en ainm_ov_ test_en ainp_uv_ test_en ainp_ov_ test_en ref_det_ test_en 0xfe r/w 0x059 gen_err_ reg_1 [7:0] reserved memmap_ crc_err rom_crc_ err spi_clk_ count_ err spi_ invalid_ read_err spi_ invalid_ write_err spi_crc_ err 0x00 r 0x05a gen_err_ reg_1_en [7:0] reserved memmap_ crc_test_en rom_crc_ test_en spi_clk_ count_ test_en spi_ invalid_ read_ test_en spi_ invalid_ write_ test_en spi_crc_ test_ en 0x3e r/w 0x05b gen_err_ reg_2 [7:0] reserved reset_ detected ext_mclk_ switch_err re - served aldo1_ psm_err aldo2_ psm_err dldo_ psm_err 0x00 r 0x05c gen_err_ reg_2_en [7:0] reserved reset_ detect_en reserved ldo_psm_test_ en ldo_psm_trip_test_en 0x3c r/w 0x05d status_reg_1 [7:0] reserved chip_error err_loc_ch4 err_loc_ ch3 err_loc_ ch2 err_loc_ ch1 err_loc_ ch0 0x00 r data sheet ad7770 rev. c | page 63 of 97 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x05e status_reg_2 [7:0] reserved chip_error err_loc_ gen2 err_loc_ gen1 err_ loc_ch7 err_loc_ ch6 err_loc_ ch5 0x00 r 0x05f status_reg_3 [7:0] reserved chip_error init_ complete err_loc_ sat_ch6_7 err_loc_s at_ch4_5 err_loc_ sat_ch2_3 err_loc_ sat_ch0_1 0x00 r 0x060 src_n_msb [7:0] reserved src_n_all[11:8] 0x00 r/w 0x061 src_n_lsb [7:0] src_n_all[7:0] 0x80 r/w 0x062 src_if_msb [7:0] src_if_all[15:8] 0x00 r/w 0x063 src_if_lsb [7:0] src_if_all[7:0] 0x00 r/w 0x064 src_update [7:0] src_ load_ source reserved src_load_ update 0x00 r/w ad7770 data sheet rev. c | page 64 of 97 register details channel 0 configuration regist er address: 0x 0 00, reset: 0x00, name: ch0_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch0_gain (r/w ) [2 :0 ] reserved [5] ch0_ref_monitor (r/w ) [3 ] reserved [4] ch0_rx (r/w ) table 45 . bit descriptions for ch0_config bits bit name settings description reset access [7:6] ch0_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 ga in = 2 10 gain = 4 11 gain = 8 5 ch0_ref_monitor channel used as reference monitor 0x0 r/w 4 ch0_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 1 configurat ion register address: 0x0 0 1, reset: 0x00, name: ch1_config afe ga in 11: gain = 8. 10: gain = 4. 01: gain = 2. 00: gain = 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch1_gain (r/w ) [2 :0 ] reserved [5] ch1_ref_monitor (r/w ) [3 ] reserved [4] ch1_rx (r/w ) table 46 . bit descriptions for ch1_config bits bit name settings description reset access [7:6] ch1_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch1_ref_monitor channel used as reference monitor 0x0 r/w 4 ch1_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w data sheet ad7770 rev. c | page 65 of 97 channel 2 configurat ion register address: 0x0 0 2, reset: 0x00, name: ch2_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch2_gain (r/w ) [2 :0 ] reserved [5] ch2_ref_monitor (r/w ) [3 ] reserved [4] ch2_rx (r/w ) table 47 . bit descriptions for ch2_config bits bit name settings description reset access [7:6] ch2_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch2_ref_monitor channel used as reference monitor 0x0 r/w 4 ch2_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 3 configurat ion register address: 0x0 0 3, reset: 0x00, name: ch3_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch3_gain (r/w ) [2 :0 ] reserved [5] ch3_ref_monitor (r/w ) [3 ] reserved [4] ch3_rx (r/w ) table 48 . bit descriptions for ch3_config bits bit name settings description reset access [7:6] ch3_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gai n = 2 10 gain = 4 11 gain = 8 5 ch3_ref_monitor channel used as reference monitor 0x0 r/w 4 ch3_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w ad7770 data sheet rev. c | page 66 of 97 channel 4 configurat ion register address: 0x0 0 4, reset: 0x00, name: ch4_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch4_gain (r/w ) [2 :0 ] reserved [5] ch4_ref_monitor (r/w ) [3 ] reserved [4] ch4_rx (r/w ) table 49 . bit descriptions for ch4_config bits bit name settings description reset access [7:6] ch4_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch4_ref_monitor channel used as reference monitor 0x0 r/w 4 ch4_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 5 configurat ion register address: 0x0 0 5, reset: 0x00, name: ch5_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch5_gain (r/w ) [2 :0 ] reserved [5] ch5_ref_monitor (r/w ) [3 ] reserved [4] ch5_rx (r/w ) table 50 . bit descriptions for ch5_config bits bit name settings description reset access [7:6] ch5_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch5_ref_monitor channel used as reference monitor 0x0 r/w 4 ch5_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w data sheet ad7770 rev. c | page 67 of 97 channel 6 configurat ion register address: 0x 0 06, reset: 0x00, name: ch6_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch6_gain (r/w ) [2 :0 ] reserved [5] ch6_ref_monitor (r/w ) [3 ] reserved [4] ch6_rx (r/w ) table 51 . bit descriptions for ch6_config bits bit name settings description reset access [7:6] ch6_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch6_ref_monitor channel used as reference monitor 0x0 r/w 4 ch6_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 7 configurat ion register address: 0x0 0 7, reset: 0x00, name: ch7_config afe ga in 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch7_gain (r/w ) [2 :0 ] reserved [5] ch7_ref_monitor (r/w ) [3 ] reserved [4] ch7_rx (r/w ) table 52 . bit descriptions for ch7_config bits bit name settings description reset access [7:6] ch7_gain afe gain 0x0 r/w 0 0 gain = 1 0 1 gain = 2 10 gain = 4 11 gain = 8 5 ch7 _ref_monitor channel used as reference monitor 0x0 r/w 4 ch7 _rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w ad7770 data sheet rev. c | page 68 of 97 disable clocks to ad c channel register address: 0x 0 08, reset: 0x00, name: ch_disable channel 7 disable channel 0 disable channel 6 disable channel 1 disable channel 5 disable channel 2 disable channel 4 disable channel 3 disable 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] ch7_disable (r/w ) [0] ch0_disable (r/w ) [6] ch6_disable (r/w ) [1] ch1_disable (r/w ) [5] ch5_disable (r/w ) [2] ch2_disable (r/w ) [4] ch4_disable (r/w ) [3] ch3_disable (r/w ) table 53 . bit d escriptions for ch_disable bits bit name settings description reset access 7 ch7_disable channel 7 disable 0x0 r/w 6 ch6_disable channel 6 disable 0x0 r/w 5 ch5_disable channel 5 disable 0x0 r/w 4 ch4_disable channel 4 disable 0x0 r/w 3 ch3_disable channel 3 disable 0x0 r/w 2 ch2_disable channel 2 disable 0x0 r/w 1 ch1_disable channel 1 disable 0x0 r/w 0 ch0_disable channel 0 disable 0x0 r/w channel 0 sync offset register address: 0x0 0 9, reset: 0x00, name: ch0_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_sync_offset (r/w ) table 54 . bit descriptions for ch0_sync_offset bits bit name settings description reset access [7:0] ch0_sync_offset channel sync offset 0x0 r/w channel 1 sync offset register address: 0x 0 0a, reset: 0x00, name: ch1_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_sync_offset (r/w ) table 55 . bit descriptions for ch1_sync_offset bits bit name settings description reset access [7:0] ch1_sync_offset channel sync offset 0x0 r/w channel 2 sync offset register address: 0x0 0 b, reset: 0x00, name: ch2_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_sync_offset (r/w ) table 56 . bit descriptions for ch2_sync_offset bits bit name settings description reset access [7:0] ch2_sync_offset channel sync offset 0x0 r/w data sheet ad7770 rev. c | page 69 of 97 channel 3 sync offset register address: 0x0 0 c, reset: 0x00, name: ch3_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_sync_offset (r/w ) table 57 . bit descriptions for ch3_sync_offset bits bit name settings description reset access [7:0] ch3_sync_offset channel sync offset 0x0 r/w channel 4 sync offset register address: 0x 0 0d, reset: 0x00, name: ch4_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_sync_offset (r/w ) table 58 . bit descriptions for ch4_sync_offset bits bit name settings description reset access [7:0] ch4_sync_offset channel sync offset 0x0 r/w channel 5 sync offset register address: 0x 0 0e, reset: 0x00, name: ch5_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_sync_offset (r/w ) table 59 . bit descriptions for ch5_sync_offset bits bit name settings description reset access [7:0] ch5_sync_offset channel sync offset 0x0 r/w channel 6 sync offset register address: 0x0 0 f, reset: 0x00, name: ch6_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_sync_offset (r/w ) table 60 . bit descriptions for ch6_sync_offset bits bit name settings description reset access [7:0] ch6_sync_offset channel sync offset 0x0 r/w channel 7 sync offset register address: 0x 0 10, reset: 0x00, name: ch7_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_sync_offset (r/w ) table 61 . bit descriptions for ch7_sync_offset bits bit name settings description reset access [7:0] ch7_sync_offset channel sync offset 0x0 r/w ad7770 data sheet rev. c | page 70 of 97 general user configu ration 1 register address: 0x 0 11, reset: 0x24 , name: general_user_config_1 if all sd channels are disabled, setting this bit high allows dclk to continue toggling soft reset 11: 1s t write. 10: 2nd write. 01: no effect. 00: no effect. power mode 1: high resolution. 0: low power (1/4) powerdown signal for internal oscillator. active low powerdown vcm buffer. active low powerdown sa. active low powerdown internal reference output buffer. active low 0 0 1 0 2 1 3 0 4 0 5 1 6 0 7 0 [7] all_ch_dis__mclk_en (r/w ) [1:0] soft_reset (r/w ) [6] pow ermode (r/w ) [2] pdb_rc_osc (r/w ) [5] pdb_vcm (r/w ) [3] pdb_sar (r/w ) [4] pdb_refout_buf (r/w ) table 62 . bit descriptions for general_user_config_1 bits bit name settings description reset access 7 all_ch_dis_mclk_en if all - channels are disabled, setting this bit high allows dclk to continue toggling . 0x0 r/w 6 powermode power mode . 0x0 r/w 0 low power (1/4) . 1 high resolution . 5 pdb_vcm power down vcm buffer . active low. 0x1 r/w 4 pdb_refout_buf power down internal reference output buffer . active low. 0x0 r/w 3 pdb_sar power down sar . active low. 0x0 r/w 2 pdb_rc_osc power down signal for internal oscillator . active low. 0x1 r/w [1:0] soft_reset soft reset . 0x0 r/w 0 0 no effect . 0 1 no effect . 10 2nd write . 11 1st write . general user configu ration 2 register address: 0x 0 12, reset: 0x09, name: general_user_config_2 sync pulse generated thru spi 1: startb pin in the control module. this bit is anded with the value on 0: generate a pulse in /sync_in pin. on startb pin in the control module, this signal is anded with the value dout drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. sets spi interface to read back sar result on sdo sdo drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. 0 1 1 0 2 0 3 1 4 0 5 0 6 0 7 0 [7 ] reserved [0] spi_sync (r/w ) [6 ] reserved [2:1] dout_drive_str (r/w ) [5] sar_diag_mode_en (r/w ) [4:3] sdo_drive_str (r/w ) table 63 . bit descriptions for general_user_config_2 bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 sar_diag_mode_en sets spi to read back sar result on sdo . 0x0 r/w data sheet ad7770 rev. c | page 71 of 97 bits bit name settings description reset access [4:3] sdo_drive_str sdo drive strength . 0x1 r/w 0 0 nominal. 0 1 strong. 10 weak. 11 extra strong . [2:1] dout_drive_str dout x drive strength . 0x0 r/w 0 0 nominal. 0 1 strong. 10 weak. 11 extra strong . 0 spi_sync sync pulse generated through spi . 0x1 r/w 0 this signal is and ed with the value on the start pin in the control module a nd generate s a pulse in the sync_in pin. 1 this bit is and ed with the value on start pin in the control module. general user configu ration 3 register address: 0x013, reset: 0x80, name: general_user_config_3 disable deglitching of convst pin 11: no deglitch circuit. 10: convst_sar deglitch 1.5 mclk. 01: reserved. 00: reserved. disables the clock qualifier check if the user requires to use an mclk signal < 265khz. enable to spi slave mode to read back adc on sdo 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:6] convst_deglitch_dis (r/w ) [0] clk_qual_dis (r/w ) [5 ] reserved [1 ] reserved [4] spi_slave_mode_en (r/w ) [3 :2 ] reserved table 64 . bit d escriptions for general_user_config_3 bits bit name settings description reset access [7:6] convst_deglitch_dis disable deglitching of convst _sar pin . 0x2 r/w 00 reserved. 01 reserved. 10 convst_sar d eglitch 1.5 / mclk. 11 no deglitch circuit. 5 reserved reserved. 0x0 r/w 4 spi_slave_mode_en enable to spi slave mode to read back adc on sdo . 0x0 r/w [3:2] reserved reserved. 0x0 r/w 1 reserved reserved. 0x0 r/w 0 clk_qual_dis disables the clock qualifier check if the user r equires to use an mclk signal < 265 khz. 0x0 r/w ad7770 data sheet rev. c | page 72 of 97 data out put format register address: 0x 0 14, reset: 0x20, name: dout_format data out format 11: 1 dout lines. 10: 1 dout lines. 01: 2 dout lines. 00: 4 dout lines. dout header format 1: crc header. 0: status header. divide mclk 111: divide by 128. 110: divide by 64. 101: divide by 32. 100: divide by 16. 011: divide by 8. 010: divide by 4. 001: divide by 2. 000: divide by 1. 0 0 1 0 2 0 3 0 4 0 5 1 6 0 7 0 [7:6] dout_format (r/w ) [0 ] reserved [5] dout_header_format (r/w ) [3:1] dclk_clk_div (r/w ) [4 ] reserved table 65 . bit descriptions for dout_format bits bit name settings description reset access [7:6] dout_format data out format 0x0 r/w 0 0 4 dout x lines 0 1 2 doutx lines 10 1 doutx lines 11 1 doutx lines 5 dout_header_format doutx header format 0x1 r/w 0 status header 1 crc header 4 reserved reserved 0x0 r/w [3:1] dclk_clk_div divide mclk 0x0 r/w 000 divide by 1 001 divide by 2 0 10 divide by 4 0 11 divide by 8 100 divide by 16 101 divide by 32 110 divide by 64 111 divide by 128 0 reserved reserved 0x0 r/w data sheet ad7770 rev. c | page 73 of 97 main adc meter and reference mux control register address: 0x015, reset: 0x00, name: adc_mux_config sd adc reference mux 11: external reference refx-/refx+. 10: external supply avdd1x/avssx. 01: internal reference. 00: external reference refx+/refx- sd adc meter mux 1001: external reference refx+/refx+. 1000: internal reference +/+. 0111: internal reference -/+. 0110: internal reference +/- 0101: external reference refx-/refx- 0100: external reference refx-/refx+. 0011: external reference refx+/refx- 0010: 280mv. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ref_mux_ctrl (r/w ) [1 :0 ] reserved [5:2] mtr_mux_ctrl (r/w ) table 66 . bit descriptions for adc_mux_config bits bit name settings description reset access [7:6] ref_mux_ctrl - adc reference mux 0x0 r/w 0 0 external reference refx+/refx ? 0 1 internal reference . 10 external supply avdd1x/avssx 11 external reference refx ? /refx+ [5:2] mtr_mux_ctrl - adc meter mux 0x0 r/w 00 10 280 mv 0011 external reference refx+/refx ? 0 100 external reference refx? /refx+ 0 101 external reference refx? /refx ? 0 110 internal reference +/? 0 111 internal reference ? /+ 1000 internal reference +/+ 1001 external reference refx+/refx+ [1:0] reserved reserved 0x0 r/w ad7770 data sheet rev. c | page 74 of 97 global diagnostics m ux register address: 0x 0 16, reset: 0x00, name: global_mux_config global sar diagnostics mux control 10101: avssx avdd4. attenuated. 10100: ref2+ avssx. 10011: ref1+ avssx. ... 00010: ref1p ref1n. 00001: dvbe avssx. 00000: au xain + au xain - 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] global_mux_ctrl (r/w ) [2 :0 ] reserved table 67 . bit descriptions for global_mux_config bits bit name settings description reset access [7:3] global_mux_ctrl global sar diagnostics mux control . 0x0 r/w 0000 0 auxain+/auxain? . 0000 1 dv be /avssx . 000 10 ref1+/ref1? . 0 00 11 ref2+/ ref2 ? . 0 0 100 ref_out/avssx . 0 0 101 vcm/avssx . 0 0 110 areg1cap/avssx . 0 0 111 areg2cap/avssx . 0 1000 dregcap/dgnd . 0 1001 avdd1a/avssx . 0 1010 avdd1b/avssx . 0 1011 avdd2a/avssx . 0 1100 avdd2b/avssx . 0 1101 iovdd/dgnd . 0 1110 avdd4/ avssx . 0 1111 dgnd/avss x . 10000 dgnd/avss x . 10001 dgnd/avssx . 10010 avdd4/avssx . 10011 ref1+/avssx . 10100 ref2+/avssx . 10101 avssx /avdd4 . attenuated. [2:0] reserved reserved. 0x0 r/w gpio configuration regist er address: 0x 0 17, reset: 0x00, name: gpio_config gpio input/output 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :3 ] reserved [2:0] gpio_op_en (r/w ) table 68 . bit descriptions for gpio_config bits bit name settings description reset access [7:3] reserved reserved 0x0 r/w [2:0] gpio_op_en gpio input/output 0x0 r/w data sheet ad7770 rev. c | page 75 of 97 gpio data register address: 0x 0 18, reset: 0x00, name: gpio_data value sent to gpio pins data read from gpio pins 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [2:0] gpio_w rite_data (r/w ) [5:3] gpio_read_data (r) table 69 . bit descriptions for gpio_data bits bit name settings description reset access [7:6] reserved reserved 0x0 r/w [5:3] gpio_read_data data read from the gpio pins 0x0 r [2:0] gpio_write_data value sent to the gpio pins 0x0 r/w buffer configuration 1 register address: 0x 0 19, reset: 0x38, name: buffer_config_1 reference buffer positive enable reference buffer negative enable 0 0 1 0 2 0 3 1 4 1 5 0 6 0 7 0 [7 ] reserved [0 ] reserved [6 ] reserved [1 ] reserved [5 ] reserved [2 ] reserved [4] ref_buf_pos_en (r/w ) [3] ref_buf_neg_en (r/w ) table 70 . bit descriptions for buffer_config_1 bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ref_buf_pos_en reference buffer positive enable 0x1 r/w 3 ref_buf_neg_en reference buffer negative enable 0x1 r/w [2:0] reserved reserved 0x0 r/w buffer configuration 2 register address: 0x 0 1a, reset: 0xc0, name: buffer_config_2 reference buffer positive precharge enable dregcap overdrive enable. reference buffer negative precharge enable areg2cap overdrive enable areg1cap overdrive enable 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 1 [7] refbufp_preq (r/w ) [0] pdb_dldo_ovrdrv (r/w ) [6] refbufn_preq (r/w ) [1] pdb_aldo2_ovrdrv (r/w ) [5 :3 ] reserved [2] pdb_aldo1_ovrdrv (r/w ) table 71 . bit descriptions for buffer_config_2 bits bit name settings description reset access 7 refbufp_preq reference buffer positive precharge enable 0x1 r/w 6 refbufn_preq reference buffer negative precharge enable 0x1 r/w [5:3] reserved reserved 0x0 r/w 2 pdb_aldo1_ovrdrv areg1cap overdrive enable 0x0 r/w 1 pdb_aldo2_ovrdrv areg2cap overdrive enable 0x0 r/w 0 pdb_dldo_ovrdrv dregcap overdrive enable 0x0 r/w ad7770 data sheet rev. c | page 76 of 97 channel 0 offset upp er byte register address: 0x 0 1c, reset: 0x00, name: ch0_offset_upper_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[23:16] (r/w) table 72 . bit descriptions for ch0_offset_upper_byte bits bit name settings description reset access [7:0] ch0_offset_all[23:16] combined offset register channel 0 0x0 r/w channel 0 offset middle byte register address: 0x 0 1d, reset: 0x00, name: ch0_offset_mid_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[15:8] (r/w) table 73 . bit descriptions for ch0_offset_mid_byte bits bit name settings description reset access [7:0] ch0_offset_all[15:8] combined offset register channel 0 0x0 r/w channel 0 offset low er byte register address: 0x 0 1e, reset: 0x00, name: ch0_offset_lower_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[7:0] (r/w) table 74 . bit descriptions for ch0_offset_lower_byte bits bit name settings description reset access [7:0] ch0_offset_all[7:0] combined offset register channel 0 0x0 r/w channel 0 gain upper byte register address: 0x 0 1f, reset: 0x00, name: ch0_gain_upper_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[23:16] (r/w) table 75 . bit descriptions for ch0_gain_upper_byte bits bit name settings description reset access [7:0] ch0_gain_ all[23:16] combined gain register channel 0 0x0 r/w channel 0 gain middl e byte register address: 0x 0 20, reset: 0x00, name: ch0_gain_mid_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[15:8] (r/w) table 76 . bit descriptions for ch0_gain_mid_byte bits bit name settings description reset access [7:0] ch0_gain_ all[15:8] combined gain register channel 0 0x0 r/w data sheet ad7770 rev. c | page 77 of 97 channel 0 gain lower byte register address: 0x 0 21, reset: 0x00, name: ch0_gain_lower_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[7:0] (r/w) table 77 . bit descriptions for ch0_gain_lower_byte bits bit name settings description reset access [7:0] ch0_gain_ all[7:0] combined gain register channel 0 0x0 r/w channel 1 offset upp er byte register address: 0x 0 22, reset: 0x00, name: ch1_offset_upper_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[23:16] (r/w) table 78 . bit descriptions for ch1_offset_upper_byte bits bit name settings description reset access [7:0] ch1_offset_all[23:16] combined offset register channel 1 0x0 r/w channel 1 offset mid dle byte register address: 0x 0 23, reset: 0x00, name: ch1_offset_mid_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[15:8] (r/w) table 79 . bit descriptions for ch1_offset_mid_byte bits bit name settings description reset access [7:0] ch1_offset_all[15:8] combined offset register channel 1 0x0 r/w channel 1 offset low er byte register address: 0x 0 24, reset: 0x00, name: ch1_offset_lower_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[7:0] (r/w) table 80 . bit descriptions for ch1_offset_lower_byte bits bit name settings description reset access [7:0] ch1_offset_all[7:0] combined offset register channel 1 0x0 r/w ad7770 data sheet rev. c | page 78 of 97 channel 1 gain upper byte register address: 0x 0 25, reset: 0x00, name: ch1_gain_upper_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[23:16] (r/w) table 81 . bit descriptions for ch1_gain_upper_byte bits bit name settings description reset access [7:0] ch1_gain_ all[23:16] combined gain register channel 1 0x0 r/w channel 1 gain middl e byte register address: 0x 0 26, reset: 0x00, name: ch1_gain_mid_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[15:8] (r/w) table 82 . bit descriptions for ch1_gain_mid_byte bits bit name settings description reset access [7:0] ch1_gain_ all[15:8] combined gain register channel 1 0x0 r/w channel 1 gain lower byte register address: 0x 0 27, reset: 0x00, name: ch1_gain_lower_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[7:0] (r/w) table 83 . bit descriptions for ch1_gain_lower_byte bits bit name settings description reset access [7:0] ch1_gain_ all[7:0] combined gain register channel 1 0x0 r/w channel 2 offset upp er byte register address: 0x 0 28, reset: 0x00, name: ch2_offset_upper_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[23:16] (r/w) table 84 . bit descriptions for ch2_offset_upper_byte bits bit name settings description reset access [7:0] ch2_offset_all[23:16] combined offset register channel 2 0x0 r/w channel 2 offset mid dle byte register address: 0x 0 29, reset: 0x00, name: ch2_offset_mid_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[15:8] (r/w) table 85 . bit descriptions for ch2_offset_mid_byte bits bit name settings description reset access [7:0] ch2_offset_all[15:8] combined offset register channel 2 0x0 r/w data sheet ad7770 rev. c | page 79 of 97 channel 2 offset low er byte register address: 0x 0 2a, reset: 0x00, name: ch2_offset_lower_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[7:0] (r/w) table 86 . bit descriptions for ch2_offset_lower_byte bits bit name settings description reset access [7:0] ch2_offset_all[7:0] combined offset register channel 2 0x0 r/w channel 2 gain upper byte register address: 0x 0 2b, reset: 0x00, name: ch2_gain_upper_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[23:16] (r/w) table 87 . bit descriptions for ch2_gain_upper_byte bits bit name settings description reset access [7:0] ch2_gain_ all[23:16] combined gain register channel 2 0x0 r/w channel 2 gain middl e byte register address: 0x 0 2c, reset: 0x00, name: ch2_gain_mid_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[15:8] (r/w) table 88 . bit descriptions for ch2_gain_mid_byte bits bit name settings description reset access [7:0] ch2_gain_ all[15:8] combined gain register channel 2 0x0 r/w channel 2 gain lower byte register address: 0x 0 2d, reset: 0x00, name: ch2_gain_lower_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[7:0] (r/w) table 89 . bit descriptions for ch2_gain_lower_byte bits bit name settings description reset access [7:0] ch2_gain_ all[7:0] combined gain register channel 2 0x0 r/w channel 3 offset upp er byte register address: 0x 0 2e, reset: 0x00, name: ch3_offset_upper_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[23:16] (r/w) table 90 . bit descriptions for ch3_offset_upper_byte bits bit name settings description reset access [7:0] ch3_offset_all[23:16] combined offset register channel 3 0x0 r/w ad7770 data sheet rev. c | page 80 of 97 channel 3 offset mid dle byte register address: 0x 0 2f, reset: 0x00, name: ch3_offset_mid_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[15:8] (r/w) table 91 . bit descriptions for ch3_offset_mid_byte bits bit name settings description reset access [7:0] ch3_offset_all[15:8] combined offset register channel 3 0x0 r/w channel 3 offset low er byte register address: 0x 0 30, reset: 0x00, name: ch3_offset_lower_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[7:0] (r/w) table 92 . bit descriptions for ch3_offset_lower_byte bits bit name settings description reset access [7:0] ch3_offset_all[7:0] combined offset register channel 3 0x0 r/w channel 3 gain upper byte register address: 0x 0 31, reset: 0x00, name: ch3_gain_upper_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[23:16] (r/w) table 93 . bit descriptions for ch3_gain_upper_byte bits bit name settings description reset access [7:0] ch3_gain_ all[23:16] combined gain register channel 3 0x0 r/w channel 3 gain middl e byte register address: 0x 0 32, reset: 0x00, name: ch3_gain_mid_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[15:8] (r/w) table 94 . bit descriptions for ch3_gain_mid_byte bits bit name settings description reset access [7:0] ch3_gain_ all[15:8] combined gain register channel 3 0x0 r/w channel 3 gain lower byte register address: 0x 0 33, reset: 0x00, name: ch3_gain_lower_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[7:0] (r/w) table 95 . bit descriptions for ch3_gain_lower_byte bits bit name settings description reset access [7:0] ch3_gain_ all[7:0] combined gain register channel 3 0x0 r/w data sheet ad7770 rev. c | page 81 of 97 channel 4 offset upp er byte register address: 0x 0 34, reset: 0x00, name: ch4_offset_upper_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[23:16] (r/w) table 96 . bit descriptions for ch4_offset_upper_byte bits bit name settings description reset access [7:0] ch4_offset_all[23:16] combined offset register channel 4 0x0 r/w channel 4 offset mid dle byte register address: 0x 0 35, reset: 0x00, name: ch4_offset_mid_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[15:8] (r/w) table 97 . bit descriptions for ch4_offset_mid_byte bits bit name settings description reset access [7:0] ch4_offset_all[15:8] combined offset register channel 4 0x0 r/w channel 4 offset low er byte register address: 0x 0 36, reset: 0x00, name: ch4_offset_lower_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[7:0] (r/w) table 98 . bit descriptions for ch4_offset_lower_byte bits bit name settings description reset access [7:0] ch4_offset_all[7:0] combined offset register channel 4 0x0 r/w channel 4 gain upper byte register address: 0x 0 37, reset: 0x00, name: ch4_gain_upper_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[23:16] (r/w) table 99 . bit descriptions for ch4_gain_upper_byte bits bit name settings description reset access [7:0] ch4_gain_ all[23:16] combined gain register channel 4 0x0 r/w channel 4 gain middl e byte register address: 0x 0 38, reset: 0x00, name: ch4_gain_mid_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[15:8] (r/w) table 100 . bit descriptions for ch4_gain_mid_byte bits bit name settings description reset access [7:0] ch4_gain_ all[15:8] combined gain register channel 4 0x0 r/w ad7770 data sheet rev. c | page 82 of 97 channel 4 gain lower byte register address: 0x 0 39, reset: 0x00, name: ch4_gain_lower_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[7:0] (r/w) table 101 . bit descriptions for ch4_gain_lower_byte bits bit name settings description reset access [7:0] ch4_gain_ all[7:0] combined gain register channel 4 0x0 r/w channel 5 offset upp er byte register address: 0x 0 3a, reset: 0x00, name: ch5_offset_upper_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[23:16] (r/w) table 102 . bit descriptions for ch5_offset_upper_byte bits bit name settings description reset access [7:0] ch5_offset_all[23:16] combined offset register channel 5 0x0 r/w channel 5 offset mid dle byte register address: 0x 0 3b, reset: 0x00, name: ch5_offset_mid_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[15:8] (r/w) table 103 . bit descriptions for ch5_offset_mid_byte bits bit name settings description reset access [7:0] ch5_offset_all[15:8] combined offset register channel 5 0x0 r/w channel 5 offset low er byte register address: 0x 0 3c, reset: 0x00, name: ch5_offset_lower_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[7:0] (r/w) table 104 . bit descriptions for ch5_offset_lower_byte bits bit name settings description reset access [7:0] ch5_offset_all[7:0] combined offset register channel 5 0x0 r/w channel 5 gain upper byte register address: 0x 0 3d, reset: 0x00, name: ch5_gain_upper_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[23:16] (r/w) table 105 . bit descriptions for ch5_gain_upper_byte bits bit name settings description reset access [7:0] ch5_gain_ all[23:16] combined gain register channel 5 0x0 r/w data sheet ad7770 rev. c | page 83 of 97 channel 5 gain middl e byte register address: 0x 0 3e, reset: 0x00, name: ch5_gain_mid_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[15:8] (r/w) table 106 . bit descriptions for ch5_gain_mid_byte bits bit name settings description reset access [7:0] ch5_gain_ all[15:8] combined gain register channel 5 0x0 r/w channel 5 gain lower byte register address: 0x 0 3f, reset: 0x00, name: ch5_gain_lower_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[7:0] (r/w) table 107 . bit descriptions for ch5_gain_lower_byte bits bit name settings description reset access [7:0] ch5_gain_ all[7:0] combined gain register channel 5 0x0 r/w channel 6 offset upp er byte register address: 0x 0 40, reset: 0x00, name: ch6_offset_upper_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[23:16] (r/w) table 108 . bit descriptions for ch6_offset_upper_byte bits bit name settings description reset access [7:0] ch6_offset_all[23:16] combined offset register channel 6 0x0 r/w channel 6 offset mid dle byte register address: 0x 0 41, reset: 0x00, name: ch6_offset_mid_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[15:8] (r/w) table 109 . bit descriptions for ch6_offset_mid_byte bits bit name settings description reset access [7:0] ch6_offset_all[15:8] combined offset register channel 6 0x0 r/w channel 6 offset low er byte register address: 0x 0 42, reset: 0x00, name: ch6_offset_lower_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[7:0] (r/w) table 110 . bit descriptions for ch6_offset_lower_byte bits bit name settings description reset access [7:0] ch6_offset_all[7:0] combined offset register channel 6 0x0 r/w ad7770 data sheet rev. c | page 84 of 97 channel 6 gain upper byte register address: 0x 0 43, reset: 0x00, name: ch6_gain_upper_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[23:16] (r/w) table 111 . bit descriptions for ch6_gain_upper_byte bits bit name settings description reset access [7:0] ch6_gain_ all[23:16] combined gain register channel 6 0x0 r/w channel 6 gain middl e byte register address: 0x 0 44, reset: 0x00, name: ch6_gain_mid_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[15:8] (r/w) table 112 . bit descriptions for ch6_gain_mid_byte bits bit name settings description reset access [7:0] ch6_gain_ all[15:8] combined gain register channel 6 0x0 r/w channel 6 gain lower byte register address: 0x 0 45, reset: 0x00, name: ch6_gain_lower_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[7:0] (r/w) table 113 . bit descriptions for ch6_gain_lower_byte bits bit name settings description reset access [7:0] ch6_gain_ all[7:0] combined gain register channel 6 0x0 r/w channel 7 offset upp er byte register address: 0x 0 46, reset: 0x00, name: ch7_offset_upper_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[23:16] (r/w) table 114 . bit descriptions for ch7_offset_upper_byte bits bit name settings description reset access [7:0] ch7_offset_all[23:16] combined offset register channel 7 0x0 r/w channel 7 offset mid dle byte register address: 0x 0 47, reset: 0x00, name: ch7_offset_mid_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[15:8] (r/w) table 115 . bit descriptions for ch7_offset_mid_byte bits bit name settings description reset access [7:0] ch7_offset_all[15:8] combined offset register channel 7 0x0 r/w data sheet ad7770 rev. c | page 85 of 97 channel 7 offset low er byte register address: 0x 0 48, reset: 0x00, name: ch7_offset_lower_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[7:0] (r/w) table 116 . bit descriptions for ch7_offset_lower_byte bits bit name settings description reset access [7:0] ch7_offset_all[7:0] combined offset register channel 7 0x0 r/w channel 7 gain upper byte register address: 0x 0 49, reset: 0x00, name: ch7_gain_upper_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[23:16] (r/w) table 117 . bit descriptions for ch7_gain_upper_byte bits bit name settings description reset access [7:0] ch7_gain all[23:16] combined gain register channel 7 0x0 r/w channel 7 gain middl e byte register address: 0x 0 4a, reset: 0x00, name: ch7_gain_mid_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[15:8] (r/w) table 118 . bit descriptions for ch7_gain_mid_byte bits bit name settings description reset access [7:0] ch7_gain all[15:8] combined gain register channel 7 0x0 r/w channel 7 gain lower byte register address: 0x 0 4b, reset: 0x00, name: ch7_gain_lower_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[7:0] (r/w ) table 119 . bit descriptions for ch7_gain_lower_byte bits bit name settings description reset access [7:0] ch7_gain all[7:0] combined gain register channel 7 0x0 r/w ad7770 data sheet rev. c | page 86 of 97 channel 0 status reg ister address: 0x 0 4c, reset: 0x00, name: ch0_err_reg channel 0 - reference detect error ain0- undervoltage error ain0+ overvoltage error ain0- overvoltage error ain0+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch0_err_ref_det (r) [4] ch0_err_ainm_uv (r) [1] ch0_err_ainp_ov (r) [3] ch0_err_ainm_ov (r) [2] ch0_err_ainp_uv (r) table 120 . bit descriptions for ch0_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch0_err_ainm_uv channel 0 ain 0 ? undervoltage error 0x0 r 3 ch0_err_ainm_ov channel 0 ain 0 ? overvoltage error 0x0 r 2 ch0_err_ainp_uv channel 0 ain 0 + undervoltage error 0x0 r 1 ch0_err_ainp_ov channel 0 ain 0 + overvoltage error 0x0 r 0 ch0_err_ref_det channel 0 reference detect error 0x0 r channel 1 status reg ister address: 0x 0 4d, reset: 0x00, name: ch1_err_reg channel 1 - reference detect error ain1- undervoltage error ain1+ overvoltage error ain1- overvoltage error ain1+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch1_err_ref_det (r) [4] ch1_err_ainm_uv (r) [1] ch1_err_ainp_ov (r) [3] ch1_err_ainm_ov (r) [2] ch1_err_ainp_uv (r) table 121 . bit descriptions for ch1_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch1_err_ainm_uv channel 1 ain 1 ? undervoltage error 0x0 r 3 ch1_err_ainm_ov channel 1 ain 1 ? overvoltage error 0x0 r 2 ch1_err_ainp_uv channel 1 ain 1 + undervoltage error 0x0 r 1 ch1_err_ainp_ov channel 1 ain 1 + overvoltage error 0x0 r 0 ch1_err_ref_det channel 1 reference detect error 0x0 r data sheet ad7770 rev. c | page 87 of 97 channel 2 status reg ister address: 0x 0 4e, reset: 0x00, name: ch2_err_reg channel 2 - reference detect error ain2- undervoltage error ain2+ overvoltage error ain2- overvoltage error ain2+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch2_err_ref_det (r) [4] ch2_err_ainm_uv (r) [1] ch2_err_ainp_ov (r) [3] ch2_err_ainm_ov (r) [2] ch2_err_ainp_uv (r) table 122 . bit descriptions for ch2_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch2_err_ainm_uv channel 2 ain 2 ? undervoltage error 0x0 r 3 ch2_err_ainm_ov channel 2 ain 2 ? overvoltage error 0x0 r 2 ch2_err_ainp_uv channel 2 ain 2 + undervoltage error 0x0 r 1 ch2_err_ainp_ov channel 2 ain 2 + overvoltage error 0x0 r 0 ch2_err_ref_det channel 2 reference detect error 0x0 r channel 3 status reg ister address: 0x 0 4f, reset: 0x00, name: ch3_err_reg channel 3 - reference detect error ain3- undervoltage error ain3+ overvoltage error ain3- overvoltage error ain3+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch3_err_ref_det (r) [4] ch3_err_ainm_uv (r) [1] ch3_err_ainp_ov (r) [3] ch3_err_ainm_ov (r) [2] ch3_err_ainp_uv (r) table 123 . bit descriptions for ch3_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch3_err_ainm_uv channel 3 ain 3 ? undervoltage error 0x0 r 3 ch3_err_ainm_ov channel 3 ain 3 ? overvoltage error 0x0 r 2 ch3_err_ainp_uv channel 3 ain 3 + undervoltage error 0x0 r 1 ch3_err_ainp_ov channel 3 ain 3 + overvoltage error 0x0 r 0 ch3_err_ref_det channel 3 reference detect error 0x0 r ad7770 data sheet rev. c | page 88 of 97 channel 4 status reg ister address: 0x 0 50, reset: 0x00, name: ch4_err_reg channel 4 - reference detect error ain4- undervoltage error ain4+ overvoltage error ain4- overvoltage error ain4+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch4_err_ref_det (r) [4] ch4_err_ainm_uv (r) [1] ch4_err_ainp_ov (r) [3] ch4_err_ainm_ov (r) [2] ch4_err_ainp_uv (r) table 124 . bit descriptions for ch4_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch4_err_ainm_uv channel 4 ain 4 ? undervoltage error 0x0 r 3 ch4_err_ainm_ov channel 4 ain 4 ? overvoltage error 0x0 r 2 ch4_err_ainp_uv channel 4 ain 4 + undervoltage error 0x0 r 1 ch4_err_ainp_ov channel 4 ain 4 + overvoltage error 0x0 r 0 ch4_err_ref_det channel 4 reference detect error 0x0 r channel 5 status reg ister address: 0x 0 51, reset: 0x00, name: ch5_err_reg channel 5 - reference detect error ain5- undervoltage error ain5+ overvoltage error ain5- overvoltage error ain5+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch5_err_ref_det (r) [4] ch5_err_ainm_uv (r) [1] ch5_err_ainp_ov (r) [3] ch5_err_ainm_ov (r) [2] ch5_err_ainp_uv (r) table 125 . bit descriptions for ch5_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch5_err_ainm_uv channel 5 ain 5 ? undervoltage error 0x0 r 3 ch5_err_ainm_ov channel 5 ain 5 ? overvoltage error 0x0 r 2 ch5_err_ainp_uv channel 5 ain 5 + undervoltage error 0x0 r 1 ch5_err_ainp_ov channel 5 ain 5 + overvoltage error 0x0 r 0 ch5_err_ref_det channel 5 reference detect error 0x0 r data sheet ad7770 rev. c | page 89 of 97 channel 6 status reg ister address: 0x 0 52, reset: 0x00, name: ch6_err_reg channel 6 - reference detect error ain6- undervoltage error ain6+ overvoltage error ain6- overvoltage error ain6+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch6_err_ref_det (r) [4] ch6_err_ainm_uv (r) [1] ch6_err_ainp_ov (r) [3] ch6_err_ainm_ov (r) [2] ch6_err_ainp_uv (r) table 126 . bit descriptions for ch6_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch6_err_ainm_uv channel 6 ain 6 ? undervoltage error 0x0 r 3 ch6_err_ainm_ov channel 6 ain 6 ? overvoltage error 0x0 r 2 ch6_err_ainp_uv channel 6 ain 6 + undervoltage error 0x0 r 1 ch6_err_ainp_ov channel 6 ain 6 + overvoltage error 0x0 r 0 ch6_err_ref_det channel 6 reference detect error 0x0 r channel 7 status reg ister address: 0x 0 53, reset: 0x00, name: ch7_err_reg channel 7 - reference detect error ain7- undervoltage error ain7+ overvoltage error ain7- overvoltage error ain7+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [0] ch7_err_ref_det (r) [4] ch7_err_ainm_uv (r) [1] ch7_err_ainp_ov (r) [3] ch7_err_ainm_ov (r) [2] ch7_err_ainp_uv (r) table 127 . bit descriptions for ch7_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r 4 ch7_err_ainm_uv channel 7 ain 7 ? undervoltage error 0x0 r 3 ch7_err_ainm_ov channel 7 ain 7 ? overvoltage error 0x0 r 2 ch7_err_ainp_uv channel 7 ain 7 + undervoltage error 0x0 r 1 ch7_err_ainp_ov channel 7 ain 7 + overvoltage error 0x0 r 0 ch7_err_ref_det channel 7 reference detect error 0x0 r ad7770 data sheet rev. c | page 90 of 97 channel 0/channel 1 dsp errors register address: 0x 0 54, reset: 0x00, name: ch0_1_sat_err channel 0 - adc conversion has exceeded limits and has been clamped channel 1 - modulator output saturation error channel 0 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 1 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 0 - modulator output saturation error channel 1 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] ch0_err_output_sat (r) [5] ch1_err_mod_sat (r) [1] ch0_err_filter_sat (r) [4] ch1_err_filter_sat (r) [2] ch0_err_mod_sat (r) [3] ch1_err_output_sat (r) table 128 . bit descriptions for ch0_1_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch1_err_mod_sat channel 1 modulator o utput s aturation e rror 0x0 r 4 ch1_err_filter_sat channel 1 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch1_err_output_sat channel 1 adc conversion has exceeded limits and is clamped 0x0 r 2 ch0_err_mod_sat channel 0 modulator o utput s aturation e rror 0x0 r 1 ch0_err_filter_sat channel 0 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch0_err_output_sat channel 0 adc conversion has exceeded limits and is clamped 0x0 r channel 2/channel 3 dsp errors register address: 0x 0 55, reset: 0x00, name: ch2_3_sat_err channel 2 - adc conversion has exceeded limits and has been clamped channel 3 - modulator output saturation error channel 2 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 3 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 2 - modulator output saturation error channel 3 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] ch2_err_output_sat (r) [5] ch3_err_mod_sat (r) [1] ch2_err_filter_sat (r) [4] ch3_err_filter_sat (r) [2] ch2_err_mod_sat (r) [3] ch3_err_output_sat (r) table 129 . bit descriptions for ch2_3_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch3_err_mod_sat channel 3 modulator o utput s aturation e rror 0x0 r 4 ch3_err_filter_sat channel 3 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch3_err_output_sat channel 3 adc conversion has exceeded limits and is clamped 0x0 r 2 ch2_err_mod_sat channel 2 modulator o utput s aturation e rror 0x0 r 1 ch2_err_filter_sat channel 2 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch2_err_output_sat channel 2 adc conversion has exceeded limits and is clamped 0x0 r data sheet ad7770 rev. c | page 91 of 97 channel 4/channel 5 dsp errors register address: 0x 0 56, reset: 0x00, name: ch4_5_sat_err channel 4 - adc conversion has exceeded limits and has been clamped channel 5 - modulator output saturation error channel 4 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 5 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 4 - modulator output saturation error channel 5 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] ch4_err_output_sat (r) [5] ch5_err_mod_sat (r) [1] ch4_err_filter_sat (r) [4] ch5_err_filter_sat (r) [2] ch4_err_mod_sat (r) [3] ch5_err_output_sat (r) table 130 . bit descriptions for ch4_5_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch5_err_mod_sat channel 5 modulator o utput s aturation e rror 0x0 r 4 ch5_err_filter_sat channel 5 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch5_err_output_sat channel 5 adc conversion has exceeded limits and is clamped 0x0 r 2 ch4_err_mod_sat channel 4 modulator o utput s aturation e rror 0x0 r 1 ch4_err_filter_sat channel 4 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch4_err_output_sat channel 4 adc conversion has exceeded limits and is clamped 0x0 r channel 6/channel 7 dsp errors register address: 0x 0 57, reset: 0x00, name: ch6_7_sat_err channel 6 - adc conversion has exceeded limits and has been clamped channel 7 - modulator output saturation error channel 6 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 7 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 6 - modulator output saturation error channel 7 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] ch6_err_output_sat (r) [5] ch7_err_mod_sat (r) [1] ch6_err_filter_sat (r) [4] ch7_err_filter_sat (r) [2] ch6_err_mod_sat (r) [3] ch7_err_output_sat (r) table 131 . bit descriptions for ch6_7_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch7_err_mod_sat channel 7 modulator o utput s aturation e rror 0x0 r 4 ch7_err_filter_sat channel 7 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch7_err_output_sat channel 7 adc conversion has exceeded limits and is clamped 0x0 r 2 ch6_err_mod_sat channel 6 modulator output saturation error 0x0 r 1 ch6_err_filter_sat channel 6 filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch6_err_output_sat channel 6 adc conversion has exceeded limits and is clamped 0x0 r ad7770 data sheet rev. c | page 92 of 97 channel 0 to channel 7 error register ena ble register address: 0x 0 58, reset: 0xfe, name: chx_err_reg_en adc conversion error test enable reference detect test enable filter saturation error test enable ainx+ overvoltage test enable enable error flag for modulator saturation ainx+ undervoltage test enable ainx- undervoltage test enable ainx- overvoltage test enable 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 1 [7] output_sat_test_en (r/w ) [0 ] ref_ det_ test_ en (r/w ) [6] filter_sat_test_en (r/w ) [1] ainp_ov_test_en (r/w ) [5] mod_sat_test_en (r/w ) [2] ainp_uv_test_en (r/w ) [4] ainm_uv_test_en (r/w ) [3] ainm_ov_test_en (r/w ) table 132 . bit descriptions for chx_err_reg_en bits bit name settings description reset access 7 output_sat_test_en adc conversion error test enable 0x1 r/w 6 filter_sat_test_en filter saturation test enable 0x1 r/w 5 mod_sat_test_en enable error flag for modulator saturation 0x1 r/w 4 ainm_uv_test_en ain x ? undervoltage test enable 0x1 r/w 3 ainm_ov_test_en ain x ? overvoltage test enable 0x1 r/w 2 ainp_uv_test_en ain x + undervoltage test enable 0x1 r/w 1 ainp_ov_test_en ain x + overvoltage test enable 0x1 r/w 0 ref_det_test_en reference detect test enable 0x0 r/w general errors regis ter 1 address: 0x 0 59, reset: 0x00, name: gen_err_reg_1 spi crc error a crc of the memory map contents is run periodically to check for errors spi invalid write address a crc of the fuse contents is run periodically to check for errors in the fuses spi invalid read address spi clock counter error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] spi_crc_err (r) [5] memmap_crc_err (r) [1] spi_invalid_w rite_err (r) [4] rom_crc_err (r) [2] spi_invalid_read_err (r) [3] spi_clk_count_err (r) table 133 . bit descriptions for gen_err_reg_1 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 memmap_crc_err a crc of the memory map contents is run periodically to check for errors 0x0 r 4 rom_crc_err a c rc of the fuse contents is run periodically to check for errors in the fuses 0x0 r 3 spi_clk_count_err spi clock counter error 0x0 r 2 spi_invalid_read_err spi invalid read address 0x0 r 1 spi_invalid_write_err spi invalid write address 0x0 r 0 spi_crc_err spi crc error 0x0 r data sheet ad7770 rev. c | page 93 of 97 general errors regis ter 1 enable address: 0x 0 5a, reset: 0x3e, name: gen_err_reg_1_en table 1 34 . bit descriptions for gen_err_reg_1_en bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 memmap_crc_test_en memory map crc error enable 0x1 r/w 4 rom_crc_test_en fuse crc test enable 0x1 r/w 3 spi_clk_count_test_en spi clock counter test enable 0x1 r/w 2 spi_invalid_read_test_en spi invalid read address test enable 0x1 r/w 1 spi_invalid_write_test_en spi invalid write address test enable 0x1 r/w 0 spi_crc_test_en spi crc error test enable 0x0 r/w general errors regis ter 2 address: 0x 0 5b, reset: 0x00, name: gen_err_reg_2 dregcap power supply error reset detected areg2cap power supply error clock not switched over areg1cap power supply error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] dldo_psm_err (r) [5 ] reset_ detected (r) [1] aldo2_psm_err (r) [4] ext_mclk_sw itch_err (r) [2] aldo1_psm_err (r) [3 ] reserved table 135 . bit descriptions for gen_err_reg_2 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 reset_detected reset detected 0x0 r 4 ext_mclk_switch_err clock not switched over 0x0 r 3 reserved reserved 0x0 r 2 aldo1_psm_err areg1cap power supply error 0x0 r 1 aldo2_psm_err areg2cap power supply error 0x0 r 0 dldo_psm_err dregcap power supply error 0x0 r ad7770 data sheet rev. c | page 94 of 97 general errors regis ter 2 enable address: 0x 0 5c, reset: 0x3c, name: gen_err_reg_2_en ldo psm trip test enable 11: 11 - run trip detect test on dregcap. 10: 10 - run trip detect test on areg2cap. 1: 01 - run trip detect test on areg1cap. 0: 00 - no trip detect test enabled. reset detect enable ldo psm test en 11: on all ldos. 11 - run power supply monitor test 10: on dregcap. 10 - run power supply monitor test 1: on aregxcap. 01 - run power supply monitor test 0: enabled. 00 - no power supply monitor test 0 0 1 0 2 1 3 1 4 0 5 1 6 0 7 0 [7 :6 ] reserved [1:0] ldo_psm_trip_test_en (r/w) [5 ] reset_ detect_ en (r/w ) [3:2] ldo_psm_test_en (r/w) [4 ] reserved table 136 . bit descriptions for gen_err_reg_2_en bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 reset_detect_en reset detect enable 0x1 r/w 4 reserved reserved 0x1 r/w [3:2] ldo_psm_test_ en ldo psm test en 0x3 r/w 0 00 no po wer supply monitor test enabled 1 01 run power supply monitor test on aregxcap 10 10 run power supply monitor test on dregcap 11 11 run power supply monitor test on all ldos [1:0] ldo_psm_trip_test_en ldo psm trip test enable 0x0 r/w 0 00 no trip detect test enabled 1 01 run trip detect test on areg1cap 10 10 run trip detect test on areg2cap 11 11 run trip detect test on dregcap error status registe r 1 address: 0x 0 5d, reset: 0x00, name: status_reg_1 an error specific to ch0_err_reg is active set high if any error bit is high an error specific to ch1_err_reg is active an error specific to ch4_err_reg is active an error specific to ch2_err_reg is active an error specific to ch3_err_reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] err_loc_ch0 (r) [5] chip_error (r) [1] err_loc_ch1 (r) [4] err_loc_ch4 (r) [2] err_loc_ch2 (r) [3] err_loc_ch3 (r) table 137 . bit descriptions for status_reg_1 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set this bit high if any error bit is high 0x0 r 4 err_loc_ch4 an error specific to ch4_err_reg is active 0x0 r 3 err_loc_ch3 an error specific to ch3_err_reg is active 0x0 r 2 err_loc_ch2 an error specific to ch2_err_reg is active 0x0 r 1 err_loc_ch1 an error specific to ch1_err_reg is active 0x0 r 0 err_loc_ch0 an error specific to ch0_err_reg is active 0x0 r data sheet ad7770 rev. c | page 95 of 97 error status registe r 2 address: 0x 0 5e, reset: 0x00, name: status_reg_2 an error specific to ch5_err_reg is active set high if any error bit is high an error specific to ch6_err_reg is active an error specific to gen_err_reg_2 is active an error specific to ch7_err_reg is active an error specific to gen_err_reg_1 is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] err_loc_ch5 (r) [5] chip_error (r) [1] err_loc_ch6 (r) [4] err_loc_gen2 (r) [2] err_loc_ch7 (r) [3] err_loc_gen1 (r) table 138 . bit descriptions for status_reg_2 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set high if any error bit is high 0x0 r 4 err_loc_gen2 an error specific to gen_err_reg_2 is active 0x0 r 3 err_loc_gen1 an error specific to gen_err_reg_1 is active 0x0 r 2 err_loc_ch7 an error specific to ch7_err_reg is active 0x0 r 1 err_loc_ch6 an error specific to ch6_err_reg is active 0x0 r 0 err_loc_ch5 an error specific to ch5_err_reg is active 0x0 r error status registe r 3 address: 0x 0 5f, reset: 0x00, name: status_reg_3 an error specific to ch0_1_sat_err reg is active set high if any error bit is high an error specific to ch2_3_sat_err reg is active fuse initialization is complete. device is ready to receive commands an error specific to ch4_5_sat_err reg is active an error specific to ch6_7_sat_err reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :6 ] reserved [0] err_loc_sat_ch0_1 (r) [5] chip_error (r) [1] err_loc_sat_ch2_3 (r) [4] init_complete (r) [2] err_loc_sat_ch4_5 (r) [3] err_loc_sat_ch6_7 (r) table 139 . bit descriptions for status_reg_3 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set high if any error bit is high. 0x0 r 4 init_complete fuse initialization is complete . device is ready to receive commands. 0x0 r 3 err_loc_sat_ch6_7 an error specific to ch6_7_sat_err register is active. 0x0 r 2 err_loc_sat_ch4_5 an error specific to ch4_5_sat_err register is active. 0x0 r 1 err_loc_sat_ch2_3 an error specific to ch2_3_sat_err register is active. 0x0 r 0 err_loc_sat_ch0_1 an error specific to ch0_1_sat_err register is active. 0x0 r decimation rate (n) msb register address: 0x 0 60, reset: 0x00, name: src_n_msb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :4 ] reserved [3:0] src_n_all[11:8] (r/w) table 140 . bit descriptions for src_n_msb bits bit name settings description reset access [7:4] reserved reserved 0x0 r [3:0] src_n_all[11:8] src n combined 0x0 r/w ad7770 data sheet rev. c | page 96 of 97 decimation rate (n) lsb register address: 0x 0 61, reset: 0x80, name: src_n_lsb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:0] src_n_all[7:0] (r/w) table 141 . bit descriptions for src_n_lsb bits bit name settings description reset access [7:0] src_n_all[7:0] src n combined 0x0 r/w decimation rate (if) msb register address: 0x 0 62, reset: 0x00, name: src_if_msb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[15:8] (r/w) table 142 . bit descriptions for src_if_msb bits bit name settings description reset access [7:0] src_if_all[15:8] src if all 0x0 r/w decimation rate (if) lsb register address: 0x 0 63, reset: 0x00, name: src_if_lsb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[7:0] (r/w) table 143 . bit descriptions for src_if_lsb bits bit name settings description reset access [7:0] src_if_all[7:0] src if all 0x0 r/w src load source and load update register address: 0x 0 64, reset: 0x00, name: src_update select which option to load an src update assert bit to load src registers into src 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] src_load_source (r/w ) [0] src_load_update (r/w ) [6 :1 ] reserved table 144 . bit descriptions for src_update bits bit name settings description reset access 7 src_load_source select s which option to load an src update 0x0 r/w [6:1] reserved reserved 0x0 r 0 src_load_update assert s bit to load src registers into src 0x0 r/w data sheet ad7770 rev. c | page 97 of 97 outline dimensions 0.50 bsc bot t om view top view pin 1 indic at or exposed pa d pin 1 indic at or 7.70 7.60 sq 7.50 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-12-2014- a 9.10 9.00 sq 8.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min 7.50 ref compliant to jedec standards mo-220-wmmd 1 64 16 17 49 48 32 33 pkg-004396 figure 121 . 64 - lead lead frame chip scale package [lfcsp] 9 mm 9 mm body and 0.75 mm package height (cp - 64 - 15) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7770 acpz ? 40c to +125c 64- lead lead frame chip scale package [lfcsp] cp - 64- 15 ad7770 acpz -rl ? 40c to +125c 64- lead lead frame chip scale package [lfcsp] cp - 64 - 15 eval - ad7770fmcz evaluation board 1 z = rohs compliant part. ? 2016 C 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12538 -0- 8/17(c) |
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